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Schaltplane und Platinenabbildungen / Circuit Diagrams and Layout of PCBs
CF 11
IC 111
PC 1297 CA (DOLBY HX-PRO)
V,
z 9°
Veo
Vee
Vinpe
PHe
Cine
Coure Voute:
Vouree
Vinvo)
CONNECTION
VOLTAGE REGULATOR
COMP REF:
SIGNAL INPUT:
PEAK HOLD:
COMP INPUT:
COMP OUTPUT:
VCA OUTPUTi1
VCA OUTPUTi2
GND
BIAS OSC INPUT
VCA OUTPUT21
VCA OUTPUT22
COMP OUTPUT2
COMP INPUT2
PEAK HOLD2
SIGNAL INPUT2
outi2
GND
COMP REF
Vcc
THERMAL
PROTECTION:
|
2
3
4
5
6
vf
uPC 1297 CA
8
Cin
Cours
Vourit V
IC 403
X 24 COOP
(EPROM)
Veo
CONTROL
SCL
SDA
INPUT/
SDA
OUTPUT
SHIFT REGISTER
NC
= NOCONNECT
Vss
= GROUND
Vee
= SUPPLY VOLTAGE
SDA = SERIAL DATA
X 24 COO
IC 501
M 34240
(4-BIT CMOS MICROCOMPUTER)
Connection
of an external
Wake
Reset
Clock Clock
Pull-down
capacitor
up input input
input output
Power supply input
Cc
CE
RESET
CNVss
Vpp
Vss
Xin
Xout
Vp
—-—@---©--9-—@—--©-—
@ - - - © - - 9 -
— -—- @-- —-—- —-—- —- —-—-—-—-—-—-
|
|
Stack register SK 3(11)}
H
Clock :
RAM
Stack register SK (11)
ROM
|
Flag P (1)
gene
128 words X 4 bits
Stack register SK ,(11
2044 words X 9 bits
'
Stack register SK
(11
|
Register B(4)|
_|Stack register SDP(8
Address
Data
'
Address
Data
| Carry
maT eal DP
Program counter PC
9
Ya)
PCH(4) | PC.(7)
Carry
Register A(4)
ove
(Accumulator)
a
——
Register D(3)
Register E(8)
Multiplexer
ass
mi oan
aia
IsioF 1)
ae
Teaser Ye iy
ler = emp +
nl
Eee
a
773
Port G(4) || Port K(1)
|
Port
S(8)— |
Port D(12)
hig
NINN
L_-@g-
- —--—_-—_-—_-
43) - REDE) €9)
—=
laid ats
DMO)
ES)
cab cai
acd
—
INT
~~
—
Sour CLK
;
Sin
S
1Ko
Interrupt input
ioe
potF
"IN
RDY?
VO port G
ee
rma
port S
~
aaa
port D,~D,,
onae
a
port Dy~D
Serial 1/O port/
Input port K
GRUNDIG Service
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