Siemens SIMATIC IPC127E Betriebsanleitung Seite 73

TCO Timer Status (TCO_STS) - Offset 64h
Bit
Range
31:18
17
16:4
3
2:0
TCO Timer Control (TCO1_CNT) - Offset 68h
Bit
Range
31:22
21:20
19:13
12
SIMATIC IPC127E
Betriebsanleitung, 11/2019, A5E44296888-AB
Default Field Name (ID): Description
&
Access
0h Reserved (reserved2): Reserved.
RO
0h Second Timeout Status (second_to_sts): PMC sets this bit to 1 to indicate that
the TIMEOUT bit had been (or is currently) set and a second timeout occured
RW/1C/
before the TCO_RLD register was written. If this bit is set an the NO_REBOOT
V
config bit is 0, then the PMC will reboot the system after second timeout. The
reboot is done by interrupting the Arc and starting a reset flow based on the
OS_POLICY. This bit is only cleared by writing a 1 to this bit or by a reset.
On some prior platforms, this field is reset on RSMRST_B, a reset signal based
on a RSMRST# pin that indicates the suspend/resume voltages are stable.
This field is reset on RSM_RST_N de-assertion. This field is not reset on cold
reset, warm reset, an Sx.
0h Reserved (reserved1): Reserved.
RO
0h Timeout (tco-timeTCOout): Bit set to 1 by PMC to indicate that the SMI was
caused by TCO timer reaching 0. Reset: On cold boot, cold reset, warm reset,
RW/1C/
and Sx.
V
0h Reserved (rsvd): Reserved.
RO
Default Field Name (ID): Description
&
Access
0h Reserved (rsvd): Reserved.
RO
0h OS Policy (os-policy): OS-based software writes to these bits to select the
policy that BIOS will use after the platform resets due the WDT. The following
RW
convention is recommended for the BIOS and OS:
00: Boot normally
01: Shut down
10: Don't load OS. Hold in pre-boot state an use LAN to determine next step.
11: Reserved
Reset on RSM_RST_N de-assertion only.
0h Reserved (reserved2): Reserved.
RO
0h TCO Lock (tco_lock): When set to 1, this bit prevents writes from changing the
TCO_EN bit (in offset 30h of Power Management I/O space). Once this bit is
RW/L
set to 1, it cannot be cleared by software writing a 0 to this location. Reset is
required to change this from 1 to 0. This bit defaults to 0. On some prior
platforms, this field is reset on cold reset. This is reset on cold boot, cold reset,
warm reset, and Sx.
Hardwarebeschreibung
10.4 Ein-/Ausgabeadressbereiche
73