Grundig XENARO GDP 5100 Serviceanleitung Seite 29

Xenaro – GDP 51..., GDP 6150
WM8720
SCKI ML/I2S
(2) (4)
256fs/384fs
BCKIN (14)
SERIAL DIGITAL
LRCIN (16)
INTERFACE FILTERS
DIN (15)
PIN NAME TYPE
1 PWDN Digital input
2 SCKI Digital input
3 TEST Digital output
4 ML/I2S Digital input
5 MC/IWL Digital input
6 MD/DM Digital input
7 RSTB Digital input
8 ZERO Digital output
9 VOUTR Analogue output
10 AGND Supply Analogue
11 AVDD Supply Analogue
12 VOUTL Analogue output
13 CAP Analogue output
14 BCKIN Digital input
15 DIN Digital input
16 LRCIN Digital input
17 MUTE Digital IO
18 MODE Digital input
19 DVDD Supply Digital
20 DGND Supply Digital
WM8721
(17)
(15) (16)
CONTROL INTERFACE
WM8721
DACDAT (3)
DIGITAL
DACLRC (4)
FILTERS
BCLK (2)
CLKIN
DIVIDER
(Div x1, x2)
(18)
PIN NAME TYPE
1 DBVDD Supply
2 BCLK Digital Input/Output
3 DACDAT Digital Input
4 DACLRC Digital Input/Output
5 HPVDD Supply
6 LHPOUT Analogue Output
7 RHPOUT Analogue Output
8 HPGND Ground Headphone GND
9 LOUT Analogue Output
10 ROUT Analogue Output
11 AVDD Supply Analogue
12 AGND Ground Analogue
13 VMID Analogue Output
14 MODE Digital Input
15 CSB Digital Input
16 SDIN Digital Input
17 SCLK Digital Input
18 MCLK Digital Input
19 DCVDD Supply
20 DGND Ground
GRUNDIG Service
MC/IWL MD/DM PWDN RSTB MODE MUTE
(5) (6) (1) (7) (18) (17)
CONTROL INTERFACE
SIGMA
MUTE/
DELTA
ATTEN
MODULATOR
SIGMA
MUTE/
DELTA
ATTEN
MODULATOR
(20) (10) (13) (11) (19)
DGND AGND CAP AVDD DVDD
DESCRIPTION
Powerdown control; low is ON, high is POWER OFF; Internal pull-down
System clock input (256 or 384fs)
Reserved
Latch enable (software mode) or input format selection (hardware mode); Internal pull-up
Serial control data clock input (software mode) or input word length selection (hardware mode); Internal pull-up
Serial control data input (software mode) or de-emphasis selection (hardware mode); Internal pull-up
Reset input – active low; Internal pull-up
Infinite zero detect – active low; Open drain type output with active pull-down
Right channel DAC output
ground supply
positive supply
Left channel DAC output
Analogue internal reference
Audio data bit clock input
Serial audio data input
Sample rate clock input
Mute control pin, input or automute output; Low is not mute, high is mute, Z is automute
Mode select pin; Low is software mode, high is hardware control; Internal pull-down
positive supply
ground supply
(14) (11) (13) (12)
+6 to -73dB
1 dB Steps
VOL/ H/P
MUTE DRIVER
DAC
DAC
VOL/
H/P
MUTE DRIVER
+6 to -73dB
1 dB Steps
(19) (1) (20)
DESCRIPTION
Digital Buffers VDD
Digital Audio Port Clock
DAC Digital Audio Data Input
DAC Sample Rate Clock
Headphone VDD
Left Channel Headphone Output
Right Channel Headphone Output
Left Channel Line Output
Right Channel Line Output
VDD
GND
Mid-rail reference decoupling point
Control Interface Selection, Pull up (on power up only)
3-Wire MPU Chip Select/ 2-Wire MPU interface address selection, active low, Pull up (on power up only)
3-Wire MPU Data Input / 2-Wire MPU Data Input
3-Wire MPU Clock Input / 2-Wire MPU Clock Input
Master Clock Input (MCLK)
Digital Core VDD
Digital GND
Platinenabbildungen und Schaltpläne / Layout of PCBs and Circuit Diagrams
PWDN
SCKI
WM8720
(3) TEST
TEST
(8) ZERO
ML/I2S
MC/IWL
MD/DM
DAC
(9) VOUTR
RSTB
ZERO
DAC (12) VOUTL
VOUTR
AGND
(5) HPVDD
DBVDD 1
(8)
HPGND
BCLK 2
DACDAT 3
(7)
RHPOUT
DACLRC 4
HPVDD 5
(10) ROUT
WM8721
LHPOUT 6
(9) LOUT 7
HPOUT
HPGND 8
(6)
LHPOUT
LOUT 9
ROUT 10
1 20 DGND
2 19 DVDD
3 18 MODE
4 17 MUTE
5 16 LRCIN
WM8720
6 15 DIN
7 14 BCKIN
8 13 CAP
9 12 VOUTL
10 11 AVDD
20
DGND
19
DCVDD
18
MCLK
17
SCLK
16
SDIN
15
CSB
14
MODE
13
VMID
12
AGND
11
AVDD
3 - 5