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Xenaro – GDP 51..., GDP 6150
Digital-Platte / Board – Interface
Setting: allows selection of 16/32 bit mode for ROM.
Pulldown resistor on AD4 is not assembled ==> 0 = 16-bits,
Pulldown resistor on AD4 is assembled
Setting hardware to specify power up strategy to software.
AD14] --> cfg_PdnMd PWR_CFG[10] R/W
cfg_PdnMd = ~AD[14]
0 = Power down option 1*
1 = Power down option 2
POWER-UP CONFIGURATION RESISTORS
MAD0
8
MAD1
7
MAD2
6
MAD3
5
MAD4
8
MAD5
7
MAD6
6
MAD7
5
MLA0
8
MLA1
7
MLA2
6
MXIO10
5
P5
FLASHCS0-
JUMPER SETTING
R85
SW DEVELOPMENT (SRAM)
R86
PRODUCTION (FLASH)
OPTIONAL
TEST FEATURE
LD1
YELLOW
" RESET "
P1
SRSTB-
LED-SMD1206-YELLOW (Test)
GRUNDIG Service
(P6)
MAD0
MAD3
MAD6
MLA2
==> 1 = 32-bits*
MXIO10
R80
0R MODEM N/A
+5.0V
R82
0R MODEM N/A
+3.3V
R75
3.3K N/A
AD4
+5.0V
R73
3.3K N/A
AD14
R74
10K (Dev)
X5.0V
TS14
XSPARE6
TS16
XSPARE8
TS18
XSPARE10
TS19
XSPARE12
AD30
AD28
AD26
AD24
AD23
AD22
AD21
AD19
AD17
RP2
AD16
33R N/A
AD0
1
AD15
AD1
2
AD2
AD14
3
AD3
4
AD13
RP3
AD12
33R N/A
AD11
AD4
1
AD5
2
AD10
AD6
3
AD7
AD8
4
AD7
AD6
AD5
AD3
AD1
RP7
33R N/A
PWE0-
LA0
1
LA1
2
LA2
3
LA0
XIO10
4
LA2
RD-
LHLD
R85
0R N/A
SRAMCS-
FLASHCS0-
XIO3
R86
0R
XIO5
XIO7
XIO9
XIO11
CONN 50X2 BOARD TO BOARD 0.8MM AMP 179030-4 (Dev)
+5.0V
THIS CONNECTOR (XBUS) IS USED FOR SW
R83
LDRST
DEVELOPMENT, FLASH PROGRAMMING AND
330R (Test)
CONNECTING WITH OTHER HW DEVELOPMENT
PLATFORMS AND LOGIC ANALYZER.
Platinenabbildungen und Schaltpläne / Layout of PCBs and Circuit Diagrams
J13
MAD1
1
2
MAD2
3
4
MAD4
5
6
MAD5
7
8
MAD7
9
10
MLA0
11
12
MLA1
13
14
15
16
-
MPWE0
17
18
MRD-
19
20
MMODEMINT
21
22
MSRSTB-
23
24
25
26
SOCKET MODEM
MANUFACTURER: AMP
P/N: 179030-4
100 PIN, 0.8MM PITCH
2
1
+5V
+5V
4
3
+5V
+5V
6
5
XSPARE5
+3.3V
+3.3V
TS15
8
7
XSPARE7
+3.3V
+3.3V
TS17
SRST-
10
9
SPARE1
SRST-
12
11
SPARE2
RSTP-
14
13
GND
GND
AD31
16
15
AD30
AD31
AD29
18
17
AD28
AD29
AD27
20
19
AD26
AD27
AD25
22
21
AD24
AD25
24
23
AD23
GND
PWE3-
26
25
AD22
PWE3-
28
27
AD21
GND
AD20
30
29
AD19
AD20
AD18
32
31
AD17
AD18
34
33
AD16
GND
PWE2-
36
35
AD15
PWE2-
38
37
AD14
GND
SCLKR
40
39
AD13
SCLK
42
41
AD12
GND
ACK-
44
43
AD11
ACK-
46
45
AD10
GND
AD9
48
47
AD8
AD9
50
49
AD7
GND
PWE1-
52
51
AD6
PWE1-
54
53
AD5
GND
AD4
56
55
AD3
AD4
AD2
58
57
AD1
AD2
AD0
60
59
GND
AD0
62
61
PWE0-
GND
ALE
64
63
GND
ALE
66
65
LA0
GND
68
67
LA1
LA2
LA1
LA3
70
69
GND
LA3
72
71
RD-
GND
LHLDA
74
73
GND
LHLDA
76
75
LHLD
GND
PCS0-
78
77
GND
PCS0-
80
79
SRAMCS-
GND
XIO1
82
81
GND
XIO1
84
83
XIO3
GND
XIO4
86
85
GND
XIO4
88
87
XIO5
GND
XIO6
90
89
GND
XIO6
92
91
XIO7
GND
XIO8
94
93
GND
XIO8
96
95
XIO9
GND
XIO10
98
97
GND
XIO10
100
99
XIO11
GND
J12
P6
RP5
33R N/A
8
1
PWE0-
P1, P5
7
2
RD-
P1, P5
6
3
MODEMINT
P1
5
4
SRSTB-
P1
AD[31:0] P1, P5
SRST- P1, P5, P2
RSTP-FPGA-
P1
" RESET "
SW1
2
1
SW-SPST-MOM-2P (Test)
Reference
IC Block Diagrams .........3-4
Oscillograms...................3-43
Analog Board GDP51 ....3-23
Analog Board GDP61
– AC3 .............................3-27
– Audio/Video.................3-29
Digital Board
– P1 ...............................3-15
– P2 ...............................3-17
– P3 ...............................3-19
– P4 ...............................3-19
– P5 ...............................3-20
– P6 ...............................3-21
Drive Board ....................3-37
Keyboard Control ...........3-33
Power Supply .................3-11
LA[3:0]
LA[3:0] P1, P5
LA3
LA2
LA1
LA0
PWE3-
PWE3- P1
PWE2-
PWE2- P1
PWE1-
PWE1- P1
PWE0-
PWE0- P1, P5
SCLKR
SCLKR P1
ACK-
ACK-
P1, P5
ALE
ALE
P1, P5
LHLDA
LHLDA P1
LHLD
LHLD
P1
RD-
RD-
P1, P5
PCS0-
PCS0- P1
XIO[11:1]
XIO[11:1] P1
3 - 21
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