Inhaltsverzeichnis
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Platinenabbildungen und Schaltpläne / Layout of PCBs and Circuit Diagrams
MIC
DAC
SPDIF
7
AOP
ADC
PCM
SPDIF
input
out
mod
SPDIF
format
HOST
MMU
async serial
UART0
peripheral
async serial
UART1
peripheral
sync serial
SSP0
peripheral
sync serial
Serial
SSP1
peripheral
Ports
6
HOST
DVD
11
control
DVD
sync
Front
detect
End
8
Data
CD-ROM
in
descramble
NAME
TYPE
PIN
Front End
DSYNC
I
213
DREQ
O
214
DCLK
I
215
DSTB
I
216
DVD[7:0]
I
*
External I/O
PCS0
O
193
XIO[14:1]
B
*
SDRAM
MD[31:0]
B
*
MA[11:0]
O
*
MA[13:12]
O
32-33
MCLK
O
22
CKE
O
24
CS0-
O
35
CS1-
O
66
RAS-
O
37
CAS-
O
38
WE-
O
39
DQM[3:0]-
O
11, 41, 42, 65
Host Interface
AD[31:0]
B
*
LA[3:0]
B
184-187
ALE
B
183
RD-
B
189
ACK-
B
161
SCLK
O
160
PWE[3:0]-
B
*
Slave Mode
LHLD
I
191
LHLDA
O
190
Comm Ports
UART1
RXD1
I
83
SSP1
SSPCLK1/CTS1-
B
87
SSPOUT1/DTR1-
B
86
SSPIN1/BAUD1
B
84
3 - 8
ASP
D-RAM
I-ROM D-ROM
VIDEC
DSP
VSD
MMU
HOST
MMU
HOST
HOST
audio
primary
freq synth
freq synth
Watchdog
system
oscillator
video
HOST
freq synth
DEMUX
Program
Stream
Demux
EDC
status
control
header
Packet
ints
decrypt
Framer
PES/SI
Depacketizer
FIFO
CSS
128x8
DESCRIPTION
DVD parallel mode Sector Sync
DVD parallel mode Data Request
Data sampling clock
Parallel mode Data Valid, serial mode Left/Right Clock
DVD drive parallel data port, pins: 217, 219-223, 225, 226
Peripheral chip select 0, generally used for enabling the program store ROM/FLASH
Programmable general purpose I/O also used as peripheral chip select, interrupt, PWM output and other
system signals, pins: 195, 197-200, 202-203, 205-209, 211
SDRAM data bus, pins: 227, 229, 231, 232, 234, 235, 236, 238, 239, 240, 2, 3, 5, 7, 8, 9, 43, 45, 46, 48, 50,
51, 52, 54, 55, 56, 58, 59, 60, 61, 63, 64
SDRAM address bus, pins: 12, 13, 15, 16, 18, 20, 21, 25, 26, 28, 29, 30
SDRAM address bus, reserved for pin compatibility with 64Mbit SDRAM
SDRAM clock
SDRAM Clock Enable
SDRAM primary bank chip select
SDRAM extension bank chip select
SDRAM command bit
SDRAM command bit
SDRAM command bit
SDRAM data byte enables
mP multiplexed address/data bus
Latched Address [3:0]
Address Latch Enable
Read
Programmable WAIT-/ACK-/RDY- control
External bus clock used for programmable host bus peripherals
Byte write enable for FLASH, EEPROM, SRAM or peripherals, pins: 145, 156, 170, 182
Bus Hold Request from external master in slave mode
Bus Hold Acknowledge in slave mode
UART1 serial data input from external serial device, used for IR receive
SSP1 clock or UART1 Clear to Send signal
SSP1 data out or UART1 Data Terminal Ready signal
SSP1 data in or 16X clock for USART function in UART1
Y line buffer
VIQ
VRP
Cr line buffer
Cb line buffer
MMU
HOST
MMU
Timer
Reset
MMU
MMU
Event
Tagger
BIU
Video
Start
I$ adr decode I$ rd mux
Code
Stream
Detector
Buffer
Write
Controller
Xenaro – GDP 51..., GDP 6150
CCIR656 Port
Video Port
NTSC/PAL
VOP
& SCART
Encoder
Scaler
Merge
Macrovision
OSD
CGMS
SPU
HOST
WSS
MMU
SDRAM
controller
address
Module
generator
Interfaces
Datapath
HOST
Arbiter
regs
circular
buffer
Interrupt
Host
Routing
Xbus interface
registers
D$ adr decodeD$ rd mux
I$ control
D$ control
I$ Tag
I$
D$ Tag
D$
256x18
1024x32
256x20
256x32
CPU
GRUNDIG Service
Y/G
C/Cb/B
Cr/R
CVBS/C
10
ctrl
12
MA
32
MD
32
AD
22
ctrl
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