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Xenaro – GDP 51..., GDP 6150
NAME
TYPE
PIN
UART0
RXD0
I
94
TXD0
B
93
RTS0
B
96
CTS0
B
95
SSP0
SSPOUT0/DTR0
B
92
SSPIN0/BAUD0
B
90
SSPCLK0/RTS1
B
88
System Interface
RSTP-
I
81
SRST-
O
80
Video Interface
CVBS/C
O
118
Y/G
O
114
C/Cb/B
O
112
SCART
CVBS2/Cr/R
O
110
IOM
O
111
VREF
I
116
RSET
O
119
COMP
O
120
VddDAC
P
108
VssDAC
P
109
Vaa3
P
113
Vaa
P
117
Vssa
P
115
Video Port
VIO[7:0]
B
126-131, 133-134 Bidirectional digital video port data bus
HSYNC
B
124
VSYNC
B
123
VIOCLK
B
122
Audio Interface
AOUT0
O
74
AOUT1
O
73
AOUT2
O
72
AOUT3
O
71
SPDIF
O
68
ACLK
O
78
PCMCLK
O
76
LRCLK
O
79
AIN
I
70
Clock Signals
CXI
I
98
CXO
O
99
OSCVdd
P
101
OSCVss
P
100
MVCKVdd
P
102
MVCKVss
P
104
ACLKVdd
P
107
ACLKVss
P
105
Test
SCEN
I
103
SCMD
I
106
PWR & GND
VDD
P
*
Vss
P
*
VDDIO
P
*
VSSIO
P
*
GRUNDIG Service
DESCRIPTION
UART0 serial data input from external serial device
UART0 serial data output to an external serial device
UART0 request to send
UART0 Clear to Send signal
SSP0 data out or UART0 Data Terminal Ready signal
SSP0 data in or 16X clock for USART function in UART0
SSP0 clock or Request To Send function in UART1
RESET_Power- from system, used to reset frequency synthesizer & rest of chip
Active low RESET signal for peripheral reset
Composite video output for NTSC/PAL or Chrominance output for S-Video
Luminance for NTSC/PAL S-Video and component output, G output for SCART
Chrominance output for NTSC/PAL S-Video, Cb output for component, Blue output for
A second CVBS output for composite, Cr output for component, Red output for SCART
Cascaded DAC differential output used to dump current into external resistor for power
Input voltage reference (1.2V typ) for output DACs
Current setting resistor of output DACs
Compensation capacitor connection
DAC Digital Power/2.5V
DAC Digital Ground
DAC Analog Power/3.3V
DAC Analog Power/2.5V
DAC Analog Ground
Bidirectional HSYNC signal for devices that do not use EAV/SAV codes
Bidirectional VSYNC signal for devices that do not use EAV/SAV codes
VCLK input/output for Video I/O Port function
Serial audio output data to audio DAC for Left & Right channels
Serial audio output data to audio DAC for Center & LFE channels
Serial audio output data to audio DAC for Surround Left & Right channels
Serial audio output data to audio DAC for Left & Right channels for down-mixed stereo
S/PDIF digital audio output
Audio interface serial data clock, common clock for DACs & ADC
Audio DAC PCM sampling clock frequency, common clock for DACs & ADC
Left/Right Channel clock, common clock for DACs & ADC
Digital audio input for digital micro
Crystal Input pin for on-chip oscillator or system input clock
Crystal Output pin for on-chip oscillator
Oscillator Power (2.5V)
Oscillator Ground
Main & Video Clock PLL Power (3.3V)
Main & Video Clock PLL Ground
Audio clock PLL Power (3.3V)
Audio clock PLL Ground
Scan Chain test enable
Scan Chain test mode
Core Power =2.5V, pins: 4, 34, 77, 89, 135, 159, 192, 212
Core & Ring Ground, pins: 17, 47, 69, 85, 121, 171, 201, 230
I/O Pad power = 3.3V, pins: 1, 10, 19, 27, 36, 44, 53, 62, 75, 91, 125, 140, 154, 169, 181, 196, 210, 224, 233
I/O Pad ground, pins: 6, 14, 23, 31, 40, 49, 57, 67, 82, 97, 132, 147, 162, 177, 188, 204, 218, 228, 237
Platinenabbildungen und Schaltpläne / Layout of PCBs and Circuit Diagrams
3 - 9
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