Aim TSX-P Series Bedienungsanleitung Seite 18

Limit Event Status Register and Limit Event Status Enable Register
These two registers are implemented as an addition to the IEEE std.488.2. Their purpose is to
allow the controller to be informed of entry to and/or exist from current limit by any output.
Any bits set in the Limit Event Status Register which correspond to bits set in the Limit Event
Status Enable Register will cause the LIM bit to be set in the Status Byte Register.
The Limit Event Status Register is read and cleared by the LSR? command. The Limit Event
Status Enable register is set by the LSE<nrf> command and read by the LSE? command.
Bit 7 ...
Bit 2 -
Bit 1 -
Bit 0 -
Status Byte Register and Service Request Enable Register
These two registers are implemented as required by the IEEE std. 488.2.
Any bits set in the Status Byte Register which correspond to bits set in the Service Request
Enable Register will cause the RQS/MSS bit to be set in the Status Byte Register, thus
generating a Service Request on the bus.
The Status Byte Register is read either by the ∗STB? command, which will return MSS in bit 6, or
by a Serial Poll which will return RQS in bit 6. The Service Request Enable register is set by the
∗SRE <nrf> command and read by the ∗SRE? command.
Bit 7 - FLT. This is the fault bit which will be set when an output fault is detected,
i.e. an execution error 002 has occurred.
Bit 6 - RQS/MSS. This bit, as defined by IEEE Std. 488.2, contains both the Requesting
Service message and the Master Status Summary message. RQS is returned in
response to a Serial Poll and MSS is returned in response to the ∗STB? command.
Bit 5 - ESB. The Event Status Bit. This bit is set if any bits set in the Standard Event Status
Register correspond to bits set in the Standard Event Status Enable Register.
Bit 4 - MAV. The Message Available Bit. This will be set when the instrument has a
response message formatted and ready to send to the controller. The bit will be
cleared after the Response Message Terminator has been sent.
Bit 3 - Not used.
Bit 2 - Not used.
Bit 1 - Not used.
Bit 0 - LIM. The Limit status bit. This bit is set if any bits set in the Limit Event Status
Register correspond to bits set in the Limit Event Status Enable Register.
Bit 3 are not used.
Set when an output trip has occurred.
Set when output enters voltage limit.
Set when output enters current limit.
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