Aim TSX-P Series Bedienungsanleitung Seite 16

bit 7 =
bit 6 =
bit 5 =
bit 4 =
bit 3 =
bit 2 =
bit 1 =
bit 0 =
Example. To return the RQS bit (bit 6 of the Status Byte Register) as a 1 when true and a 0 when
false in bit position 1 in response to a parallel poll operation send the following commands
The parallel poll response from the generator will then be 00H if RQS is 0 and 01H if RQS is 1.
During parallel poll response the DIO interface lines are resistively terminated (passive
termination). This allows multiple devices to share the same response bit position in either wired-
AND or wired-OR configuration, see IEEE 488.1 for more information.
Power on Settings
Most instrument settings are stored in non-volatile ram and will remain unchanged while power is
off. The following instrument status values are set at power on:
Status Byte Register
* Service Request Enable Register
Standard Event Status Register
* Standard Event Status Enable Register
Limit Event Status Register
* Limit Event Status Enable Register
Execution Error Register
Query Error Register
* Parallel Poll Enable Register
* Registers marked thus are specific to the GPIB section of the instrument and are of
limited use in an ARC environment.
The standby state will be set and the instrument will be in local with the keyboard active. A
complete self-test will be performed just after power up and this will determine the values in the
Failed Output Register and the state of the FLT bit in the Status Byte Register.
Due to the non-volatile storage the power on settings are essentially modified by any command,
local or remote, which changes any value not listed above. If a defined state is require at start up
by the controller the *RST command should be issued which will load the settings as listed in the
description of that command.
If for any reason an error is detected at power up in the non-volatile ram a warning will be issued
and all settings will be returned to their default states as for a *RST command.
Status Reporting
This section describes the complete status model of the instrument. Note that some registers are
specific to the GPIB section of the instrument and are of limited use in an ARC environment.
X don't care
1
1 Parallel poll enable
0
Sense - sense of the response bit; 0 = low, 1 = high
?
? bit position of the response
?
∗PRE 64
then PPC followed by 69H (PPE)
<pmt>,
= 0
= 0
= 128 (pon bit set)
= 0
= 0 (Then set to show new limit status)
= 0
= 0
= 0
= 0
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