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A
X
4
B
-
5
3
3
/
A
X
4
B
-
5
3
3
N
O
n
l
i
n
e
-
H
a
n
d
b
u
c
h
A
X
4
B
-
5
3
3
/
A
X
4
B
-
5
3
3
N
O
n
l
i
n
e
-
H
a
n
d
b
u
c
h
Bus Master IDE (DMA mode) ........................................................................................................................................ 91
CNR (Communication and Networking Riser)................................................................................................................ 92
CODEC (Coding and Decoding) .................................................................................................................................... 92
DDR (Double Data Rated) SDRAM ............................................................................................................................... 92
DIMM (Dual In Line Memory Module) ............................................................................................................................ 93
DMA (Direct Memory Access)........................................................................................................................................ 93
ECC (Error Checking and Correction) ........................................................................................................................... 93
EDO (Extended Data Output) Memory .......................................................................................................................... 93
EEPROM (Electronic Erasable Programmable ROM).................................................................................................... 94
EPROM (Erasable Programmable ROM) ...................................................................................................................... 94
EV6 Bus ........................................................................................................................................................................ 94
FCC DoC (Declaration of Conformity) ........................................................................................................................... 94
FC-PGA (Flip Chip-Pin Grid Array) ................................................................................................................................ 95
Flash ROM .................................................................................................................................................................... 95
FSB (Front Side Bus) Clock .......................................................................................................................................... 95
2
C Bus .......................................................................................................................................................................... 95
IEEE 1394 ..................................................................................................................................................................... 96
Parity Bit ....................................................................................................................................................................... 96
PBSRAM (Pipelined Burst SRAM)................................................................................................................................. 97
6
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