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WF-CD77H/E
CP-CD77
1X1337AF
YM3015
CLOCK.
SMP1
SMP2
sp
re @_uet
FORM
FORM
PRIORITY
DIGITAL
DETECT
SHIFT
SELECT
ADRESS
OSC
BC
(8*96BIT)
(7*128BIT)
M50422P
N
SaENSsgRRRaKRS
'unl
N
x
o
s)
a}
va
qacscaqaqaqg
agoa
nin
E
FF
a
a
a
z
:
8
S
fe
Se eee2 22lslsy
wo
G2
8
OVER
ie
SLICE
LEVE
PHASE
re
Lene
FLOW
>
CONTROL
COMPARATOR
LIMITTER
IREE
I
+
REO
|
CIRC DECORDER
FREQUENCY
OUTPUT
DIGITAL FILTER
COMPARATOR
[|
CONTROL
poe
|
DECORD
SYCLK (19)
8)DFPAS
PROTECTOR
EFM
TIMING
+?
DO
CONTROL
|
65 LRCK
EFFK @3
me:
WOCK
EFM
DSCK
DEMODULATOR
Pusch
DASEL
69 DOFK
ee
TIMING CONTRO 6
Ons
aie
8:
SYS
S/S | ATT | BCON|BRAKIMUTE]
TIMER 50421
éac
BESET
Fe = Sy
67) CcLemi
MICRO COMPUTER
INTERFACE
TEST
{9-4}
Figure 43 BLOCK DIAGRAM OF IC
9
a
3
TEST)
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