Sharp WF-CD77H/E Serviceanleitung Seite 43

WF-CD77H/E
CP-CD77
€) FUNCTION TABLE OF IC
M50422P
Pin Terminal 1/0 Funct
No. Name cd
Word clock for D/A converter motor drive
1 DWDCKO
3 EMP
4
|
O Emphasis code output Emphasis provided= 1
PWM1 (eo) Disc motor PWM driving output 1,
5 PWM2 oO Disc motor PWM driving output 2, +
6 TEST I Test mode selection input Normal playback = 0
7 DASEL1 I D/A interface control input
8 DEPAS | Digital filter control input Digital filter bus = 1
9 DASEL2 I D/A interface control input
MSD | Micro-computer interface, serial data input
11 MCK | Micro-computer interface, shift clock input
12 MLA ! Micro-computer interface, data latch clock input
13 ACLR I Micro-computer interface, resistor clear input Clear=0 SS timer reset = 1 MUTE.S/S.BCOM = 0
14 HFD I Playback signal omission signal input
15 HF j Playback signal input
16 IREF t Ditection/PLL circuit reference current input
17 TLC (e) Slice level control output
18 LPF \/O PLL loop filter connection terminal
19 SYCLK oO Frame synchronous state output Synchronous state = 1
20 VDD2 I Ditection/PLL circuit Power supply for analog section 5V
22 DRD (@) Low disc rotating state output
23 EFFK oO EFM frame clock output, Duty = 50 %
24 _{ SCOR oO Sub-code synchronous signal output SO+S$1
25 CRCF e) CRC check result output of sub-code O, CRCOK=1
26 SCCK I Shift clock input for sub-code serial output
I Enable input of sub-code parallel output P-S ch, O=High impedance
29 VSS2 I GND, Same electric potential as that of VSS1
30 SBCW (e) Sub-code W ch output
31 SBCV Oo Sub-code V ch output
32 SBCU {e) Sub-code U ch output
33 SBCT oO Sub-code T ch output
34 SBCS Oo Sub-code S ch output
[35 [sack [0 [Sub-code Ach output ——SSSSSSSSSS
36 SBCQ oO Sub-code Q ch output
37 SBCP ie) Sub-code P ch output
38 RAS oO Raw address strobe signal output
40 RDB2 1/0 External memory data input/output 2
42 RDB1 1/O External memory data input/output 1
EE RDB4 1/0 External memory data input/output 4
44 CAS oO Column address strobe signal output
45 RDB3 Vo External memory data input/output 3
46 WE 10) Write enable signal output
48 RAD1 oO External memory address output 1
49 RAD2 oO External memory address output 2
50 RAD3 ie) External memory address output 3
51 RAD7 oO External memory address output 7
52 RAD4 0 External memory address output 4
53 RAD5 ie) External memory address output 5
E |_RAD6 fe) External memory address output 6
55 4 RADO (@) External memory address output 0
56 VDD1 I Power supply 5 V
57 EST2 O Error status 2, C2 uncorrectable decoder data detection = 1
58 EST1 to" Error status 1, C2 decoder error detection = 1
59 C846 Oo Clock output, 8.4672 MHz
| 60 C423 ie) Clock output, 4.2336 MHz
61 C16MI | Frequency 1/2-divider input Built-in feedback resistance for 1/2 VDD bias voltage generation
62 C8MO fe) Frequency 1/2-divider output
63 {_X1 | Quartz oscillator input External clock input possible Built-in feedback resistance
64 xO _10 Quartz oscillator output
65 vssi I GND, Same electric potential as that of VSS2
66 DOFK fe) OSC frame clock output, 7.35 kHz duty = 50 %
67 DO Oo D/A convertor, serial data output
[ 69 WDCK oO D/A converter word clock APTL when DASEL = 1
70 LRCK (e) D/A converter left clock, right clock, APTL when DASER = 1
72 DSCK (e) D/A converter, shift clock