Werbung
www.freeservicemanuals.info
UMS 11 ... UMS 12-S
IC-Blockschaltpläne / IC Block Diagrams
24
23
22
21
20
19
18
AM
OSC
AFC
AFC
AM
LOW
OUT
OSC
CUT
IN
DEMOD
ALC
AM
AM
AM
RF.AMP
MIX
OSC
BUFF
AGC
LA1832M
AM
AM
DET .
IF
LEVEL
DET
AM/FM
COMP
IF
BUFF
S-CURVE
AM/FM
TUNING
DRIVE
FM
FM
DET
IF
AM
FM
REG
GND
FM-DET
AM
AM
TU.LED
ST.LED
MIX
REG
GND
FM IF-IN
IF
1
2
3
4
5
6
7
LB 1641
T.S.D
O.C.P
MOTOR
MOTOR
DRIVE
DRIVE
FWD / REV / STOP
CONTROL LOGIC
1
2
3
4
5
6
7
8
9
48
47
46
45
44
43
42
41
40
39
38
49
+
+
+
+
50
51
RVref
RVref
RVref
RVref
52
+
53
+
54
RVref
55
56
+
+
57
58
59
LVref
+
60
61
LVref
LVref
LVref
LVref
62
63
+
+
+
+
64
1
2
3
4
5
6
7
8
9
10
11
GRUNDIG Service
Schaltpläne und Druckplattenabbildungen / Circuit Diagrams and Layout of PCBs
17
16
15
14
13
R
L
MPX
VCO
FLPET
OUT
OUT
IN
2
Serial
DECODER
Data in
STEREO
MUTE
SW
15
Output
STEREO
DRIVE
Enable
TRIG
FF
FF
FF
VCO
PILOT
DET16
SW
PHASE
DET
Vcc
AM/FM
PHASE
PILOT
3
8
9
10
11
12
Clock
1
Strobe
10
1
2
37
36
35
34
33
SW R1
GND
SW P1
32
+
31
30
29
XIN
1
RVref
28
20
XOUT
LC 75394 NE
27
1 /
FMIN
14
26
25
AMIN
13
24
CE
2
23
DI
3
2
22
C
B
CL
4
21
I / F
LVref
DO
5
20
V
15
POWER
19
DD
ON
RESET
18
19
V
SS
17
12
13
14
15
16
UMS 11 ... UMS 12-S
Latch 1
Register Stage 1
Clock
Clock
Strobe
Clock
Clock
Strobe
Strobe
Clock
Clock
Strobe
2
Latch 2
Register Stage 2
3
Register Stage 3
Latch 3
4
Register Stage 4
Latch 4
5
Register Stage 5
Latch 5
6
Register Stage 6
Latch 6
7
Register Stage 7
Latch 7
8
Register Stage 8
Latch 8
Clock
Clock
Strobe Strobe
Clock
Clock
MC 14094 B
Strobe
Strobe
Inverter
µPC 1330 HA
Comparator
3
4
5
6
7
8
9
CONT
GND
VCC
SW P2
GND
SW R2
REFERENCE
PHASE DETECTER
16
DIVIDER
CHARGE PUMP
17
UNLOCK
SWALLOW COUNTER
DETECT OR
1/16.1/17 4bits
2
18
12bits programmable
DRIVER
UNIVERSAL
DATA SFEET REGISTER
11
COUNTER
LATCH
LC 72131 M
12
6
7
8
9
10
I02
B01
B02
B03
B04
I01
3 - 5
GRUNDIG Service
Digitized in Heiloo, Holland
Schaltpläne und Druckplattenabbildungen / Circuit Diagrams and Layout of PCBs
3-State Buffer 1
DD
Q1
4
IN1
9
NF1
8
75
Q2
5
3-State Buffer 2
Q3
3-State Buffer 3
6
Bias
circuit
Q4
GND
3-State Buffer 4
7
11
Q5
3-State Buffer 5
14
Q6
IN2
13
3-State Buffer 6
13
Q7
NF2
3-State Buffer 7
12
14
75
Q8
11
3-State Buffer 8
Clock
Q´
12
10
Clock
Clock
Clock
S
9
ANTI
57kHz
RECONSTRUCTION
4
ALIASING
BANDPASS
FILTER
MUX
FILTER
(8th ORDER)
8
SCOUT
CONSTAS LOOP
CLOCKED
7
VARIABLE AND
COMPARATOR
CIN
FIXED DIVIDER
SAA 6579
5
V
p1
V
DDA
CLOCK
REFERENCE
3
REGENERATION
V
VOLTAGE
ref
AND SYNC
V
SSA
6
PD
NF
Pre Out
AIN
7
6
AOUT
300k
180k
-
Ch2
+
CH2/A
8
IFIN
-
CH1/A
1
Ch1
+
300k
180k
2
3
NF
Pre Out
30/7/2014
10
7
DC
Vcc
Ripple filter,
impulse noise
prevention circuit
BS1
6
Current limiter circuit
+
OUT1
CH 1
5
-
30k
GND
4
Thermal shroff
Overvoltage
protection
protection circuit
circuit
GND
3
Current limiter circuit
+
OUT2
CH2
2
-
BS2
1
30k
Standby switch
LA 4550
ST
13
14
12
V
OSCI
OSCO
DDD
OSCILLATOR
QUALITY BIT
1
AND
GENERATOR
QUAL
DIVIDER
BIPHASE
DIFFERENTIAL
SYMBOL
2
DECODER
DECODER
RDDA
16
RDCL
TEST LOGIC AND OUTPUT
15
SELECTOR SWITCH
T57
MODE
TEST
V
SSD
9
10
11
VCC
CG
Out
NF
5
4
14
15
180k
300k
-
Ch2
+
16
Rec In
13
ALC
ALC
-
9
Rec In
TA 8142
Ch1
+
180k
300k
12
11
10
Gnd.
Rec Out
NF
3 - 6
Werbung
