Tuner; Audio Path - Grundig STR 600 AR Serviceanleitung

STR 600 AP
Pin 28, 29:
The system clock is generated by an oscillator whose frequency is
determined by Q1402 (4MHz). A proportion of this signal is fed through
CC2025 and CR2025 and is used to provide clock for IC2100-(35).
Pin 60:
Timer output, "High" when a timer recording is programmed, LED
D86001 on the keyboard control unit illuminates.
Pin 61:
Data output to the Remote Cinch socket, e. g. for data link transfer.
Pin 62:
LED output to Standby indicator on the keyboard control unit.
Pin 63:
Switching voltage U switches the 22kHz frequency, IC2100-(29) to
22kHz
IC1655-(1) thus superimposing the "LNC Power" supply for driving the
LNC's. This 22kHz output signal can optionally also be pulse-modu-
lated with a DiSEqC Protocol.
Pin 64:
Switching voltage U to select the polarity, horizontal or vertical,
14/18V A
of voltage-controlled polarotors; "High" = horizontal.
Pin1:
Switching voltage U to switch off the LNC supply.
LNC OFF
Pin 2:
Switching voltage U to switch off the secondary supplies.
Standby
Pin 13:
Data input from the Remote Cinch socket for remote control
(e. g. Timer operation) by a video recorder.
Pin 14:
Motor current detection.
Pin 15:
Control input for the Tuner-AGC and Display.
Pin 19:
Scans whether there is a sync signal fed out from the sync signal
detector circuit IC1331. If the signal is too low or poor the µP switches
to the internal synchronising signal and the screen background be-
comes blue.
With the "green" key on the remote control handset it is possible to
force the background into synchronisation.
Pin 21:
AV switching voltage input for evaluation of the switching voltage on pin
8 of the decoder socket. If "AV IN1" is at high level the video signal is
fed back to the receiver via the connected descrambler.
Pin 22:
AV switching voltage input for evaluation of the switching voltage on pin
8 of the VCR socket. At high level "AV IN 2" the VCR signal is looped
through to the TV receiver (matrix).
Pin 23:
Stand-by switch
Pin 24:
Control voltage U for TV Tuner frequency control, contact 1.
AFC TV
Pins 47, 48:
System data and clock lead (I 2
Processor IC2100, OSD Processor CIC1331, Memory-CIC1141.
Pin 49:
AV 2 switching voltage generation for pin 8 of the VCR socket
Pin 50:
Output for driving the motor.
Pin 51:
Output for driving the motor.
Pin 52:
Acknowledgement signal input from keyboard control processor
IC86020.
Pin 53/54:
Data bus for controlling the keyboard control processor IC86020.
Pin 37:
Enable signal CS (Chip Select OSD) for the OSD Controller IC1331.
OSD
Pin 38:
RGB/TV switching voltage for changing over the Scart sockets (ma-
trix). When the RGB/TV switching voltage is at "High", CT1270,
CT1276 switch the TV receiver to RGB mode.
Pin 39:
AV 3 switching voltage generation to pin 8 of the TV-socket.
Pin 40/41:
Serial clock and data lead to drive clock CIC1120
Pin 43:
Output to mechanical polarizer
Pin 44:
0/12V switching.
Pin 32:
Output for driving a magnetic polarizer at the output of IC1300.
GRUNDIG Service
C-bus) to control the Tuner, Video
Schaltungsbeschreibung / Circuit Description
Pin 31:
Actuator input for the motor pulses.
2.2 Non Volatile Memory
NVM CIC1140 is a serial EEPROM and contains all factory and user
programmable data to configure the receiver (channel table, deviation,
polarity etc.).

3. Tuner

All functions within the tuner are controlled from CIC1401 via I
The IF signals from the LNC, in the range 950MHz to 2150MHz, are
supplied to the aerial inputs.
The LNC inputs are AC-coupled into a variable amplifier whose gain is
adjusted automatically by the AGC to ensure a constant level at the
input to the FM Demodulator. At the output contact 4 of the tuner the
baseband signal is available together with the 25Hz energy dispersal
waveform signal.
To improve the picture quality resulting from a noisy transmitter signal
a "threshold" circuit can be activated in the tuner via the menu.

4. Audio Path

Note to the Audio Demodulator Block Diagram :
Where two pin numbers are given two circuits exist, one for each stereo
channel. The first number is for the Right channel.
Audio Demodulator Block Diagram
IC1100 S TV0056A
23
FM in G1
Level
Detector 1
AGC
42,26
Level
AMPLOCK 46 , 4 1
Detector 2
The FM audio demodulator is of the Phase Locked Loop (PLL) type.
FM signals in the tuner Baseband Video signal are filtered by the
bandpass CC2014, L2014, CC2016, L2016, L2019, CC2017, CR2017,
L2017 which removes unwanted Video components from FM in.
It is important that the drive level of the signals being demodulated is
fixed so that the output amplitude from the demodulator can be
predicted. To help achieve this the input signal passes through a gain
controlled amplifier G1, whose gain is set by one of two level detectors.
When a signal is first selected Level Detector 1, which senses the
combined FM signal amplitude, is used to set G1 to an approximately
correct gain. Once PLL lock has been reached Level Detector 2 is used
which accurately monitors the actual signal level within the working PLL.
When a new audio carrier is being selected the PLL must be tuned to the new
frequency. To do this S1 is closed and the Voltage Controlled Oscillator
(VCO) is adjusted by means of the Frequency Synthesiser. The VCO
frequency is read by the Frequency Counter. Once the VCO is on frequency
S1 is opened and the VCO locks onto the incoming carrier of the same
frequency. The control loop feedback signal at the input of G2 carries the FM
modulation. The gain of G2 can be controlled to handle different FM
deviations. Loop stability is maintained by the PLL filter.
Control of all functions in the Demodulator is via the I
from IC1401.
4.1 Noise Reduction System (NRS)
The NRS consists of a peak level detector and a controlled low pass
filter. Audio for each channel to its peak detector is band limited by an
external bandpass filter, and centred on the transistors CT2073,
CT2078.
C-bus.
2
PLL
SDA
{
Filter
I 2 C Bus
SCL
47,39
30 31
To Audio
Processi ng
G2
V/I
90
VCO
0
S1
Frequen cy
Frequen cy
Synt hesizer
Counter
49,38
C-PUMP
C-bus (SDA, SCL)
2
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