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About the interface cards
*SRE?
Reads the Service Request Enable Register
*STB?
Reads the Status Byte Register, which is cle-
ared after reading
Service Request (SRQ) generation
The GPIB controller automatically handles the actions that
are triggered by the bit rsv in the status register STB.
After generating a service request and subsequent query
with *STB? from the host, the register is cleared.
The scheme is illustrated in the diagramm below.
A SRQ is generated as soon as the bit rsv in the Status Byte
register (STB) is set and the corresponding bits for events
that can cause a SRQ are activated in the Service Request
Enable Register (SRE).
Which events can cause a service request is selected with
the Service Request Enable Register by the command *SRE
<CHAR>.
The status register STB consists of these bits:
Bit 0:
Not used
Bit 1:
Not used
Enable
Positive transition
Negative transition
Condition
CC
CV
CP
CR
Reduce Power
Fct. at start
Fct. stepping
Fct. running
Input
/
Output
on
Output Enable
U = User defined
D = Set after power on
z = State of the indicated information
OPC
OPC = OPeration Complete bit
EXE= EXecution Error
QYE
QYE= QuerY Error
DDE
CME= CoMmand Errors
EXE
DDE= Device Depend Error
CME
Power on
Enable
Positive transition
Negative transition
Condition
0
MODE_A
1
MODE_B
2
MODE_AB
3
MODE_BAT
4
MODE_CR1
5
MODE_CR2
6
MODE_CV
7
8
LOCAL
9
REMOTE
10
EXTERNAL
11
12
Function mode
13
14
© 009, Elektro-Automatik GmbH & Co. KG
Questionable Status
QUES
Event
0
z
0
1
D
0
1
z
0
1
D
0
2
z
0
1
D
0
3
z
0
1
D
0
4
0/1
z
0/1
0/U
0
5
z
0
0/0
0/U
0
6
z
0
0/0
0/U
0
7
z
0
0/0
0/U
0
OR
8
0
0
0
0
0
9
0
0
0
0
0
10
0
0
0
0
0
11
z
1
1
D
0
12
z
0/1
0/1
0/U
0
13
0
0
0
0
0
14
0
0
0
0
0
Standard Event Status
Register
ESR
Condition
Enable
Event
0
z
1
0
1
0
0
0
2
z
1
0
3
z
1
0
OR
4
z
1
0
5
z
1
0
6
0
0
0
7
z
1
0
Operation Status
OPER
Event
0/z
0
0/1
0/D
0
0/z
0
0/1
0/D
0
0/z
0
0/1
0/D
0
0/z
0
0/1
0/D
0
0/z
0/1
0/1
0/D
0
0/z
0/1
0/1
0/D
0
0/z
0/1
0/1
0/D
0
0
0
0
0
0
OR
z
0
1
D
0
z
0
1
D
0
z
0
1
D
0
0
0
0
0
0
z
1
1
U
0
0
0
0
0
0
0
0
0
0
0
Bit :
err, Error queue full; this queue is cleared by reading
it and the bit is also reset. The list can hold up to 4
of the last errors
Bit 3:
ques, Questionable status register is active (on or
more events have occured)
Bit 4:
Not used
Bit 5:
esr, the standard Event Status Register (ESR), mas-
ked by the Event Status Enable Register (ESE), is
signalising that one or more events have occured
Bit 6:
rsv, always active
Bit 7:
oper, signalises, that one or more events have
occured and are stored in the Operation Status
Register
The event bits of the various registers report to the STB, if
events have occured that are enabled to be reported, by the
corresponding bits in the enable registers (*ESE, *SRE resp.
STAT:QUES:ENAB, STAT:OPER:ENAB).
OUTPUT Buffer
data
data
data
data
err
mav
ques
esr
mss
oper
Legend:
CC/CV/CP/CR = currently active regulation mode
Reduce Power = power derating active (PSI 9000 series only)
Fct. at start/running/stepping = function manager status
Input
/
Output
on = Input resp. output of the device is on
Output enable = auto-on for the output is activated
MODE_A/B/AB/BAT = actual operation mode, chosen by the rotary switch
MODE_CR1/CR = currently selected resistance range (CR1 is the smaller one)
LOCAL = device is in local mode, remote control is not allowed
REMOTE = device is remotely controlled by a digital interface card
EXTERNAL = device is controlled by the analogue interface card resp. the
built-in analog interface
Function mode = function manager active
Error Queue
Error
<>0
Error
0
Service
Request
STATUS
Enable
STB
SRE
0
0
0
1
0
0
2
1
1
3
1
1
OR
4
0
0
5
1
1
6
1
7
1
1
rsv
Service Request
Generation
EN
66
- Quicklinks:
- Ethernetkarten If-E1 und If-E
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