Inhaltsverzeichnis
Werbung
K-CDP 65
U201 - CXD2518Q
Pin
Name
I/O
Beschreibung
1
SCOR
O
Master PLL VCO control voltage input
2
SBSO
O
Analop power supply for DSP
3
EXCK
I
EFM signal input
4
SQSO
O
Constant current input of asymmerty compensation circuit
5
SQCK
I
Asymmetry compensation circuit comparator voltage input
6
MUTE
I
High: Mute; Low: release
7
SENS
O
SENS output to CPU
8
XRST
I
System reset. Reset when Low
9
DATA
I
Serial data input from CPU
10
XLAT
I
Latch input from CPU. Serial data is latched at the falling edge.
11
CLOK
I
Serial data transfer clock input from CPU
12
Vss
GND
13
SEIN
I
Sense input from SSP
14
CNIN
I
Track jump count signal input
15
DATO
O
Serial data output to SSP
16
XLTO
O
Serial data latch output to SSP. Latched at the falling edge.
17
CLTO
O
Serial data transfer clock output to SSP.
18
TEST2
I
Test pin; normally Vdd
µC extended interface (input B).
19
SPOB
I
µC extended interface (input C).
20
SPOC
I
µC extended interface (input D).
21
SPOD
I
µC extended interface (output).
22
XLON
O
23
FOK
I
Focus OK input. Used for SENS output and the servo auto sequencer.
24
MON
O
Spindle motor on/off control output.
25
MDP
O
Spindle motor servo control
26
MDS
O
Spindle motor servo control
GFS is sampled at 460 Hz; when GFS is high, this pin outputs a high signal.
27
LOCK
O
If GFS is low eight consecutive samples, this pin outputs low.
28
TEST
I
Test pin. Normally GND.
29
FILO
O
Master PLL (slave = digital PLL) filter output
30
FILI
I
Master PLL filter input.
31
PCO
O
Master PLL charge pump output.
32
Vdd
Digital power supply for DSP.
33
AVSS1
Analog GND for DSP.
34
CLTV
I
Master PLL VCO control voltage input.
35
AVDD1
Analog power supply for DSP.
36
RF
I
EFM signal input.
37
BIAS
I
Constant current input of asymmetry compensation circuit.
38
ASYI
I
Asymmetry compensation circuit comparator voltage input.
39
ASYO
O
EFM full-swing output (low = Vss, high = VdDD).
40
ASYE
I
compensation off; high: asymmetry compensation on.
41
WDCK
O
D/A interface for 48-bit slot. Word clock (2FS).
42
LRCK
O
D/A interface for 48-bit slot. LR clock (FS).
43
LRCKI
I
LR clock input for DAC. 48-bit slot)
44
PCMD
O
D/A interface. Serial data (two´s complement, MSB first)
45
PCMDI
I
Audio data input for DAC. (48-bit slot)
46
BCK
O
D/A interface. Bit clock.
47
BCKI
I
Bit clock input for DAC. (48-bit slot)
48
GTOP
O
GTOP output. Is used to monitor the frame sync protection status.(High: sync protection window off)
XUGF output. It ´s a negative pulse for the frame sync derived from the EFM signal.
49
XUGF
O
It´s the signal before sync protection.
XPCK output. It´s the inverse of the EFM PLL clock.
50
XPCK
O
The PLL is designed so that the falling edge and the EFM signal transition point coincide.
51
GFS
O
GFS output. It goes high when the frame sync and the insertion protection timing match.
52
RFCK
O
RFCK output.It´s derived from the crystal accuracy. This signal has a cycle of 136µ.
53
Vss
GND
54
C2PO
O
C2PO output. It represents the data error status.
XRAOF output. It´s generated when the 16k RAM exceeds the ±4F jitter margin.
55
XROF
O
56
MNT3
O
MNT3 output
57
MNT1
O
MNT1 output
58
MNT0
O
MNT0 output
59
FSTT
O
2/3 frequency divider output for Pins 73 and 74.
60
C4M
O
4.2336 MHz output.
61
DOUT
O
Digital OUT output
62
EMPH
O
Outputs high signal when the playback disc has emphasis, low signal when no emphasis.
63
EMPHI
I
DAC de-emphasis on/off. High: on; Low: off
64
WFCK
O
WFCK (write frame clock) output
65
ZEROL
O
No-sound data detection output; high when "no audio" data is detected (Left channel)
66
ZEROR
O
No-sound data detection output; high when "no audio" data is detected (Right channel)
67
DTSI
I
Test pin 1 for DAC; normally low.
68
VDD
Digital power supply for DAC.
69
LPWM
Left channel PWM output. (Forward phase)
70
NLPWM
Left channel PWM output. (Reverse phase)
71
AVDD2
Power supply for left channel PWM driver.
72
AVDD3
Power supply for crystal.
73
XTAI
33.8688 MHz crystal oscillation circuit input.
74
XTAO
33.8688 MHz crystal oscillation circuit output.
75
AVSS3
GND for crystal.
76
AVSS2
GND for PWM driver
77
NRPWM
Right channel PWM output. (Reverse phase)
78
RPWM
Right channel PWM output. (Forward phase)
79
DTS2
DAC test pin 2; normally low.
80
DTS3
DAC test pin 3; normally low.
GRUNDIG Service
Platinenabbildung und Schaltplan / Layout of PCB and Circuit Diagram
3-7
Werbung
Inhaltsverzeichnis
