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Platinenabbildung und Schaltplan / Layout of PCB and Circuit Diagram
ICs
U101 - CXA1782Q
Pin
Name
I/O
Beschreibung
1
FEO
I
Focus error amplifier output. Connected internally to the FZC comparator input.
2
FEI
I
Focus error input
3
FDFCT
I
Capacitor connection pin for defect time constant.
4
FGD
I
Ground this pin through a capacitor when decreasing the focus servo high-frequency gain.
5
FLB
I
External time constant setting pin for increasing the focus servo low frequency.
6
FE_O
O
Focus drive output
7
FE_M
I
Focus amplifier negative input pin
8
SRCH
I
External time constant setting pin for generating focus servo waveform
9
TGU
I
External time constant setting pin for switching tracking high-frequency gain
10
TG2
I
External time constant setting pin for switching tracking high-frequency gain
11
FSET
I
High cut off frequency setting pin for focus and tracking phase compensation amplifier
12
TA_M
I
Tracking amplifier negative input pin.
13
TA_O
O
Tracking drive output
14
SL_P
I
Sled amplifier non-inversed input.
15
SL_M
I
Sled amplifier negative input pin
16
SL_O
O
Sled drive output
17
ISET
I
Setting pin for focus search, Track jump and Sled kick current
18
VCC
19
CLK
I
Serial data transfer clock input from CPU (no pull up resistance)
20
XLT
I
Latch input from CPU (no pull up resistance)
21
DATA
I
Serial data input from CPU (no pull up resistance)
22
XRST
I
Reset input; reset at low. (no pull up resistance)
23
C OUT
O
Track number count signal output
24
SENS
O
Outputs FZC, DFCT, TZC, gain, balance, and other according to the command from CPU
25
FOK
O
Focus OK comperator output.
26
CC2
O
Input pin for the DEFECT buttom hold output capacitance-coupled.
27
CC1
I
DEFECT bottom hold output
28
CB
I
Connection pin for DEFECT bottom hold capacitor
29
CP
I
Connection pin for MIRR hold capacitor. MIRR comparator non-inversed input.
30
RF_I
I
Input pin for the RF summing amplifier output capacitance-coupled.
31
RF_O
O
RF summing amplifier output. Eye pattern check point.
RF summing amplifier inversed input.
32
RF_M
I
The RF amplifier gain is determined by the resistance connected between this pin and RFO pin.
33
LD O
O
APC amplifier output
34
PHD
I
APC amplifier input
35/36
PHD1/2
I
RF I-V amplifier inversed input. Connect these pins to the photo diode A+C and B+D pins.
37
FE_Bias
I
Bias adjustment of focus error amplifier.
38/39
F/E
I
F I-V and E I-V amplifier inversed input. Connect these pins to photo diodes F and E.
40
EI
I-V amplifier E gain adjustment. (When not using automatic balance adjustment)
41
VEE
42
TEO
O
Tracking error amplifier output.
43
LPFI
I
Comparator input for balance adjustment
44
TEI
I
Tracking error input
45
ATSC
I
Window comparator input for ATSC detection.
46
TZC
I
Tracking zero-cross comparator input.
47
TDFCT
I
Capacitor connection pin for defect time constant.
48
VC
O
(VCC+VEE)/2 DC voltage output.
3-5
K-CDP 65
Platinenabbildung und Schaltplan / Layout of PCB and Circuit Diagram
U101 - CXA1782Q
U601 - BA3571F
GRUNDIG Service
3-6
K-CDP 65
GRUNDIG Service
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