Werbung
WF-CD77H/E
CP-CD77
M50422P
Pin
Terminal
No.
Name
DWDCKO
EMP
4
PWMI
5
PWM2
6
TEST
7
DASELI
8
DEPAS
9
DASEL2
10
MSD
11
MCK
12
MI-A
13
ACLR
14
HFD
15
16
IREF
17
TLC
18
LPF
19
SYCLK
20
VDD2
22
DRD
23
EFFK
24
SCOR
CRCF
25
26
SCCK
27
SCOE2
28
SCOEI
29
vss2
30
SBCW
31
SBCV
32
SBCU
33
SBCT
34
SBCS
35
SBCR
36
SBCQ
37
SBCP
38
RAS
40
RDB2
42
RDBI
43
RDB4
44
CAS
45
RDB3
46
WE
48
49
RAD2
50
RAD3
51
RAD7
52
RAD4
53
RAD5
54
RAD6
55
RADO
56
VDDI
57
EST2
58
ESTI
59
C846
60
C423
61
Cl 6Ml
62
C8MO
63
Xl
64
xo
65
vssl
66
DOFK
67
DO
69
WDCK
70
LRCK
72
DSCK
FUNCTION
1/0
Function
Word clock for D/A converter
Emphasis code output Emphasis provided = 1
Disc motor PWM driving output I ,
o
o
Disc motor PWM driving
Test mode selection
D/A interface control input
Di ital filter control input Digital filter bus = I
D/A interface control input
Micro-computer
interface, serial data input
Micro-computer
interface, shift clock
Micro-computer
interface, data latch clock
Micro-computer
interface, resistor clear input Clear=O
Playback signal omission
Playback signal input
Ditection/PLL circuit reference current input
o
Slice level control output
1/0
PLL loop filter connection
o
Frame synchronous
Ditection/PLL circuit Power supply for analog section 5V
o
Low disc rotating state output
o
EFM frame clock output, Duty
o
Sub-code
synchronous
o
CRC check result output of sub- code Q, CRCOK= I
Shift clock input for sub-code
Enable input of sub-code parallel output P-S ch, 0=High
Enable input of sub-code
GND, Same electric
o
Sub-code
W ch output
o
Sub-code
V ch output
o
Sub-code
U ch output
o
Sub-code
T ch output
o
Sub-code
S ch output
o
Sub-code
R ch output
o
Sub-code
Q ch output
o
Sub-code
P ch output
o
Raw address strobe signal output
1/0
External memory data input/output 2
1/0
External memory data input/output 1
1/0
External memory data input/output 4
Column address strobe signal output
o
1/0
External memory data input/output 3
Write
enable
signal
o
o
External memory address output 1
o
External memory address output 2
o
External memory address output 3
o
External memory address output 7
o
External memory address output 4
External memory address output 5
o
External memory address output 6
o
External memory address output O
Power supply 5 V
o
Error status 2, C2 uncorrectable
o
Error status 1, C2 decoder
o
Clock output, 8.4672 MHz
o
Clock output, 4.2336 MHz
Frequency1/2-divider input Built-in feedback resistancefor 1/2 VDD bias voltage generation
Frequency 1/2-divider output
o
Quartz oscillator
input External clock
Quartz oscillator
output
o
GND, Same electric
o
OSC frame clock output, 7.35 kHz duty — 50 0/0
D/A convertor, serial data output
o
D/A converter
word clock APTL when DASEL— I
o
D/ A converter left clock, right clock, APTL when DASER = I
o
D/A converter,
shift clock
o
TABLE
OF
motor drive
output 2, +
input Normal playback
= O
input
input
signal input
terminal
state output Synchronous
state = 1
50 %
signal output SO+SI
serial output
parallel output T -W ch, 0=High
potential as that of VSSI
output
decoder data detection
error
detection
I
input possible Built-in feedback
potential as that of VSS2
—54
SS timer reset —
- 1 MUTE.S/S.BCOM
impedance
impedance
— 1
resistance
O
Werbung
