Dual C 828 Serviceanleitung Seite 4

Das Kippglied IC 404 (C 434, R 431, D 417, R 430) ist durch das Sper-
ren von Q 403 in seine Ausgangslage gebracht und der Ausgang von
IC 404, Pin 4 ist auf HIGH Pegel, damit wird der Oszillator stummge-
schaltet. Nach dem Betatigen der Playtaste Rechtslauf oder Linkslauf
(Reverse) wird das vom Prozessor ausgegebene LOW Signal tiber die Ent-
koppeldioden D 420 (FF) oder D 421 (Rewind) auf das Kippglied IC 404,
Pin 1 geschaltet. Damit kippt der Ausgang IC 404 Pin 4 verzégert auf
LOW Pegel, der HF-Osziltator wird freigegeben. Mit dieser Schaltungs-
maf&snahme wird ein versehentliches Anléschen verhindert.
Reverse
Nach dem Betatigen der Playtaste Linkslauf = Reverse, gibt !C 401 an
Pin 20 ein
LOW Signal an das Verzdgerungsglied
IC 404 Pin 8/9.
Nach ca. 200 ms wird durch ein LOW Signal am Ausgang von IC 404
Description of functions C 828
Analog section
Playback
The voltage from the soundhead (approximately 300 MV during play-
back of the DIN reference level) is first of ail amplified by transistors
Q 101 and O 102 and correspondingly equalized with the negative feed-
back network R 166, R 169 and C 141. The Playback frequency res-
ponse in the treble frequency range can be corrected by modifying the
soundhead resonance with capacitors C 131,C 132,and C 135 (connec-
tion or disconnection). From 315 Hz to 4 kHz, the playback frequency
response is linearized with VR 102 (set at the factory). Switchover of
the playback equalization from 120 Us to 70 Us is caused by transistor
Q 103 becoming forward-biased. The playback level is set separately
for each head system with the VR 105 and VR 106 at the cinch output
socket to 550 mV during playback of the Dolby reference level {200
nWb/m). This setting is necessary for perfect functioning of the Dolby
circuit.
Via the A-W switch S 1 — 3, the playback signal is routed to the Dolby
circuit 1C 102, pin 5. If the Dolby selector switch S 8 — 1 is switchea-
off, the signal is amplified linearly by approximately 26 dB within the
Dolby circuit, whilst amplification is frequency and 4evel-depended
when the Dolby switch is activated. The output signal is routed from ~
pin 7 (IC 102) via the A-W switch S 1 — 7 to the headphcne output
stage IC 103 pins 3 and 4, to the cinch output and, via the A-W switch
S 1-5, to the DIN socket.
In order to prevent switching noises from reaching the output sockets,
the output signa! is shorted with transistor Q 107 and the input of the
recording amplifier is connected to 0 V with Q 110. The high signal for
muting is generated on the drive contro! board in the case of the follo-
wing functions: fast forward, rewind and stop.
Recording
Three different sources are provided for recording. The line input is
deactivated when the DIN input is used. The signal coming from the
line or DIN input is deactivated by connecting a mono or stereo micro-
phone. The signa! at the Mic input is amplified with the noise free IC
101, whilst the signal at the DIN input is amplified with Q 601. The
signal from the line input is routed directly to the modulation divider
VR 101. From here, it is routed via the AW switch S 1 ~ 3 to the input
pin 5 of the Dolby circuit {C 102. The MPX filter is connected with
S 7 — 1 in order to suppress any residual pilot tone when recording
radio broadcasts.
Within the Dolby processor, the signal is branched to two different
outputs, pin 3 and pin 7 of IC 102. The signal, uninfluenced by the
Dolby process from pin 3, is routed during recording to the monitor
output (line), the display and headphone amplifier via the A-W switch
S 1-7. The signal from pin 7 reaches the recording amplifier (Q 112
and © 113) via the A-W switch S 1 — 9. The recording current is set
separately for each head system with VR 107 and VR 108. It is connec- ©
ted with QO 108 and Q 109, which depend on the setting of the reverse
switch S 2 — 8, and the level and equalization are matched to varying
tape types via transistors Q 111, Q 114 to O 119. Via the trap circuit
L 103, the recording signal is routed to the soundhead and the bias is
mixed to it with VR 109 and VR 110. By connecting the resistors
R 301 to R 310 by means of the tape type selector S 3 Fe,S 4Cr,S5
FeCr and S 6 Met, the RF oscillator is influenced in such a way that an
optimum operating point is obtained for the various tape types. The
oscillator is muted with a HIGH signal at the base of Q 305. The erase
current is set with VR 111. During playback mode, the DIN input is
isolated from the monitor signal with A-W switch S 1 — 5.
Recording level display
The output signal is routed to the headphone amplifier 1C 103 both
during recording and playback. The signal for the display amplifier
(Q 104) is decoupled from the output of IC 103 (pin 6) with C 151.
Stummschaltung
Reverse switch $ 2
Device control
Reset
inputs
DLL
A contactless infrared waveguide system is used. The infrared emitter
LED 506 is driven with the freely oscillating oscillator 1C 402 and the
transistor Q 401 with a period of T = 1 ms, f = 1 kHz. This clocking
method ensures perfect operation in the face of constant light and in-
terfering reflections. By means of the photo-transistor Q 501, the light ;
pulses are converted into electrical pulses and processed by the compa-
rator IC 402. If the beam of light is interrupted (DLL ON}, a wave sha-
ped HIGH level is applied to the output of IC 402 pin 7 for the dura-
tion of the interruption, and is switched by C 406, R 417 and D 401 to
LOW level. This LOW signal is also applied when the cassette sensor
S 512 is closed (cassette removed) and Q 501 is negative-biased. When
the LOW signal is applied to pin 37 (IC 401), the processor recognizes
DLL on = cassette removed. The stop function is executed, the LED
STOP flashes, during playback mode the RECORD function is cancel-
led and the motors are switched-off. In play mode, the direction of mo-
tion is stored, the corresponding LED continues to light up and , after inser-
tion of a cassette, the previously selected mode PLAY becomes effective.
The oscillator signal from IC 402 is decoupled at pin 1 by C 410 and,
via transistor Q 405, reaches the interrupt input of the processor (refer
to limit switch-off) .
Limit switch-off