Abbreviations - Grundig cdp 200 Serviceanleitung

Schaltpläne und Druckplattenabbildungen / Circuit Diagrams and Layout of PCBs
Abkürzungen / Abbreviations
TDA1301 – DSIC2 (Digital Servo IC 2)
Pin Name Direction Description
µP → DSIC2
1 RESET reset input
DSIC2 → HF-preamp
2 Laser On/Off switches laser supply on/off
3 Gnd GND ground (analog part)
4 VRH reference input for A/D converter
HF-preamp → DSIC2
5 D1 unipolar current input (central diode signal input)
HF-preamp → DSIC2
6 D2 unipolar current input (central diode signal input)
HF-preamp → DSIC2
7 D3 unipolar current input (central diode signal input)
8 Vref GND reference input for A/D converter
HF-preamp → DSIC2
9 D4 unipolar current input (central diode signal input)
HF-preamp → DSIC2
10 R1 unipolar current input (satelite diode signal input)
HF-preamp → DSIC2
11 R2 unipolar current input (satelite diode signal input)
12 VDD +3.5 supply for DSIC2 (analog part)
13 XTLR selection of oscillator gain
14 TS1 GND test input 1
15 TS2 GND test input 2
DSIC2 → µP, SHOARMA
16 OTD off track detection
17 CLO not connected clock output
18 XTLO oscillator output
signal processor → SHOARMA
19 XTLI oscillator input
20 VDD +3.5 supply for DSIC2 (digital part)
21 GND GND ground (digital part)
DSIC2 → Servo Driver
22 Track radial actuator output
DSIC2 → Servo Driver
23 Focus focus actuator output
DSIC2 → Motor Driver
24 Slide slide output
µP → DSIC2
25 SILD serial interface load
µP → DSIC2
26 SICL serial interface clock
µP ↔ DSIC2
27 SIDA serial interface data
28 VDD +3.5 supply for DSIC2 (digital part)
TDA1302T – HF-PREAMPLIFIER AND LASER SUPPLY CIRCUIT
Pin Name Direction Description
HF-preamp → DSIC2
1 O4 output of current amplifier 4
HF-preamp → DSIC2
2 O6 output of current amplifier 6
HF-preamp → DSIC2
3 O3 output of current amplifier 3
HF-preamp → DSIC2
4 O1 output of current amplifier 1
HF-preamp → DSIC2
5 O5 output of current amplifier 5
HF-preamp → DSIC2
6 O2 output of current amplifier 2
DSIC2 → HF-preamp
7 LDon control pin for switching the laser on/off
laser power control → HF-preamp
8 Vddl laser supply voltage
HF-preamp → signal processor
9 Vrfe equalized output voltage of sum signal of amplifiers 1...4
10 Vrf not connected unequalized output
11 HG GND control pin for gain switch
signal processor → HF-preamp
12 LS control pin for double speed switch (switches equalization)
13 C external capacitor (bandwidth of ALPC)
14 Adj reference input
15 GND GND 0V supply, substrate connection
HF-preamp → laser diode
16 Lo current output to laser diode
monitor diode → HF-preamp
17 MI laser monitor diode input
18 Vdd +3.5 positive supply voltage
19 I2 GND photo detector input 2 (not used)
diode array → HF-preamp
20 I5 photo detector input 5 (satellite)
diode array → HF-preamp
21 I1 photo detector input 1 (central)
diode array → HF-preamp
22 I3 photo detector input 3 (central)
diode array → HF-preamp
23 I6 photo detector input 6 (satellite)
diode array → HF-preamp
24 I4 photo detector input 4 (central)
TDA1305T – DAC
Pin Name Direction Description
1 VDDA +3.5 supply voltage (analog part)
2 VSSA GND ground (analog part)
3 TEST1 GND test input 1
SHOARMA → DAC
4 BCK I2S bit clock input
SHOARMA → DAC
5 WS I2S word select input
SHOARMA → DAC
6 DATA I2S data input
7 CKSL1 GND clock selection 1
8 CKSL2 GND clock selection 2
9 VSSD GND ground (digital part)
10 VDDD +3.5 supply voltage (digital part)
11 TEST2 GND test input 2
signal processor → DAC
12 XIN system clock input
13 XOUT not connected
14 VDDX +3.5 supply voltage (digital part)
15 VSSX GND ground (digital part)
16 CDEC not connected system clock output
17 DEEM1 GND deemphasis on/off
18 DEEM2 GND deemphasis on/off
uP → DAC
19 MUSB mute control input (active low)
20 DSMB +3.5 double speed mode control input (active low)
uP → DAC
21 ATSB 12dB attenuation control input (active low)
DAC → sound control
22 VOL left channel output
23 FILTCL capacitor for left channel 1st order filter function
24 FILTCR capacitor for left channel 1st order filter function
DAC → sound control
25 VOR right channel output
26 VREF internal reference voltage input for output channels
27 VSSO GND ground (operational amplifier)
28 VDDO +3.5 supply voltage (operational amplifier)
2 - 11
CDP 200 Schaltpläne und Druckplattenabbildungen / Circuit Diagrams and Layout of PCBs
SAA7346 – SHOARMA (SHOck Absorbing RaM Addresser)
Pin Name Direction
signal processor → SHOARMA
1 CFLG
signal processor → SHOARMA
2 KILL
signal processor → SHOARMA
3 SCLI
signal processor → SHOARMA
4 WCI
signal processor → SHOARMA
5 SDI
6 CONFIG +3.5
signal processor → SHOARMA
7 CLKIN
8 TMS not conected
DSIC2 → SHOARMA
9 OTD
10 RCD2
SHOARMA → µP
11 SSD
SHOARMA → µP
12 RSB
SHOARMA → µP
13 S_NSF
µP → SHOARMA
14 RESET
SHOARMA ↔ µP
15 SIDA
µP → SHOARMA
16 SICL
µP → SHOARMA
17 SILD
18 FILL not conected
SHOARMA → mute circuit
19 KILLOUT
SHOARMA → DAC
20 SDO
SHOARMA → DAC
21 SCLO
SHOARMA → DAC
22 WCO
23 VDD +3.5
24 VSS GND
SHOARMA → DRAM
25...34 A0-A9
SHOARMA → DRAM
35 OE
SHOARMA → DRAM
36 RAS
SHOARMA → DRAM
37 CAS
SHOARMA → DRAM
38 WE
SHOARMA ↔ DRAM
39...42 D0-D3
43 VSS GND
44 VDD +3.5
SAA7345 – SIGNAL PROCESSOR CD6
Pin Name Direction
signal processor → DAC
1 CL11
2 DOBM not connected
3 V1 not connected
inner switch → signal processor
4 V2
5 Test2 GND
6 Test1 GND
signal processor → data slicer
7 ISLICE
HF-preamp → signal processor
8 HFIN
HF-preamp → signal processor
9 HFREF
→ signal processor
10 IREF
11 VDDA +3.5
12 VSSA GND
X-Tal → signal processor
13 CRIN
signal processor → X-Tal
14 CROUT
15 VDD1 +3.5
16 VSS1 GND
signal processor → DSIC2
17 CL16
18 MISC not connected
signal processor → SHOARMA
19 DATA
signal processor → SHOARMA
20 WCLK
signal processor → SHOARMA
21 SCLK
signal processor → motor control
22 MOTOR1
signal processor → motor control
23 MOTOR2
signal processor → motor control
24 V5
signal processor → motor control
25 V4
signal processor → HF-preamp
26 V3
signal processor → mute circuit
27 KILL
µP → signal processor
28 PORE
29 CLA not connected
µP ↔ signal processor
30 DA
µP → signal processor
31 CL
µP → signal processor
32 RAB
signal processor → SHOARMA
33 CFLG
34...42 connected to GND
43 VSS2
44 VDD2
GRUNDIG Service 2 - 12
Description
correction flag input
kill input
multiple speed I2S bit clock input
multiple speed I2S word clock input
multiple speed I2S data input
external DRAM select (H=4Mbit, L=1Mbit)
16.9344MHz system clock input
test mode select
off track detector input
DRAM read cycle devide by 2
shock detector output
rotational shock detector output
synthetic new subcode frame flag output
reset enable input (active low)
µP interface data line (bidirectional)
µP interface clock input
µP interface read/write
FIFO writing enable output
kill output (active low, open drain)
I2S data output
I2S bit clock output
I2S word clock output
positive power supply
ground supply
DRAM address bus outputs
DRAM enable output (active low)
DRAM row address strobe output (active low)
DRAM column address strobe output (active low)
DRAM write enable output (active low)
DRAM data bus (bidirectional)
ground supply
positive power supply
Description
11.2896MHz clock output (3-state)
digital bi-phase mark output (3-state)
versatile input pin of signal processor
versatile input pin of signal processor
test input of signal processor
test input of signal processor
current feedback from internal data slicer
comparator signal input
comparator signal input
reference current pin (nom. VDD/2)
supply (analog) of signal processor
supply (analog) of signal processor
crystal/resonator input of signal processor
crystal/resonator output of signal processor
supply for I/O-buffers of signal processor
supply for I/O-buffers of signal processor
16.9344MHz clock output of signal processor
general purpose DAC output (3-state)
serial data output of signal processor (3-state)
word clock output of signal processor (3-state)
serial bit clock output of signal processor (3-state)
motor output1 of signal processor; versatile (3-state)
motor output2 of signal processor; versatile (3-state)
versatile output pin of signal processor
versatile output pin of signal processor
versatile output pin of signal processor (open drain)
kill output; programmable (open drain)
power-on reset enable input (active low)
4.2336MHz microprocessor clock output
interface data I/O-line
interface clock input line
interface R/W and acknowledge input
correction flag output (open drain)
digital supply for internal logic of signal processor
digital supply for internal logic of signal processor
CDP 200
GRUNDIG Service