Inhaltsverzeichnis
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GRUNDIG Service
Name
Type
Audio
adc
I
adata[3:0]
O
alrclk
O
amclk
O
aoclk
O
lec958
O
aiclk_xin
I
aiclk_xout
O
aud_pll_filt
O
Video
avid[5:0]
O
iref
O
bias
O
comp
O
vclk
B
vd[0]
B
vd[1]
B
vd[2]
B
vd[3]
B
vd[4]
B
vd[5]
B
vd[6]
B
vd[7]
B
vhs_n
B
vvs_n
B
DVD-DSP / IDE
cs0_n
O
cs1_n
O
csel
O
da[2:0]
O
dd[0]
B
dd[1]
B
dd[2]
B
dd[3]
B
dd[7:4]
B
dd[15:8]
B
dior_n/sos
B
diordy/stb
I
diow_n/err
B
dmack_n
O
dmarq/dack
I
irq14
I
irq15
I
Other
VDD(core)
P
GND(core)
P
VDD(pads)
P
GND(pads)
P
Le
O
reset_n
I
sclk_xin
I
sclk_xout
O
mpeg_pll_filt
O
arm_pll_filt
O
tck
I
tdi
I
tdo
B
test_n
I
tms
I
trst_n
I
Pin
Description AML3250
50
Audio data in
46, 47, 48, 49
Audio data out
45
Left/right clock
52
Master clock
44
Data clock
51
IEC958 output
89
Audio clock XTAL pin, Connect a 14.318MHz crystal or drive with an oscillator (5MHz to 40MHz).
90
Audio clock XTAL pin, Connect a 14.318MHz crystal. Can be left open if aiclk_xin is driven by an oscillator.
72
Audio PLL filter pin (820pF to ground)
*
Video encoder analog DAC output, pins: 55, 56, 59, 60, 64, 65
57
Current reference
58
Bias voltage
61
Compensation
37
Video clock
40
Video D0, Address[8], UART RTS, GPIO[16].
41
Video D1, Address[9], UART RI, GPIO[17]
43
Video D2, Address[10], UART DTR, GPIO[18]
106
Video D3, Address[11], UART DSR, GPIO[19]
105
Video D4, Address[12], UART DCD, GPIO[20]
104
Video D5, Address[13], UART CTS, GPIO[21]
103
Video D6, Address[14], UART TxD, GPIO[22]
102
Video D7, Address[15], UART RxD, GPIO[23]
38
Horizontal sync
39
Vertical sync
188
Chip select 0
186
Chip select 1
194
Cable select
189, 190, 191
Address
202
IDE/DVD-DSP D0 (CD-Data in CD-DSP mode)
203
IDE/DVD-DSP D1 (CD-LRCLK in CD-DSP mode)
204
IDE/DVD-DSP D2 (CD-BCLK in CD-DSP mode)
205
IDE/DVD-DSP D3 (CD-C2PO in CD-DSP mode)
1, 2, 206, 207
IDE/DVD-DSP D[7:4]
3...5, 7...11
IDE D[15:8]
201
IDE dior_n, DVD-DSP sos
198
IDE diordy, DVD-DSP strobe
200
IDE diow_n, DVD-DSP error
185
IDE DMA acknowledge
197
IDE DMA request DVD-DSP dack
196
Interrupt HD0
195
Interrupt HD1
*
2.5V power supply, pins: 12, 26, 42, 54, 63, 66, 68, 69, 76, 91, 112, 131, 161, 169, 183, 192, 208
*
2.5V ground, pins: 6, 17, 20, 36, 53, 62, 67, 70, 71, 73, 75, 78, 79, 88, 107, 118, 136, 147, 165, 179, 187
*
3.3V power supply, pins: 23, 82, 124, 141, 175
*
3.3V ground, pins: 31, 129, 173, 199
193
No connect
156
Active low chip RESET. This pin must be held low for at least 10ms after power has been supplied to the
chip. There are several pins that use the rising edge of this signal to configure the chip.
80
MPEG clock XTAL pin. Connect a 14.318MHz crystal or drive with an oscillator (5MHz to 40MHz)
81
MPEG clock XTAL pin, Connect a 14.318MHz crystal. Can be left open if sclk_xin is driven by an oscillator.
77
MPEG PLL filter
74
158
JTAG, ICD, test pin
160
JTAG, ICD, test pin
157
JTAG, ICD, test pin
154
JTAG, ICD, test pin
159
JTAG, ICD, test pin
155
JTAG, ICD, test pin
2 - 14
GDP 2200
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