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Schaltungsbeschreibung / Circuit Description
7. Video Processing
7.1 Video Gain Control
Baseband Video from the Tuner section is ac coupled into a controlled
amplifier whose gain can be set to give the desired Video amplitude.
On receivers with an internal decoder this value is preset to suit its
requirements . On other models it is available to the user as a contrast
control. The range of adjustment is 0 to 12.8dB in 0.2dB steps.
7.2 Video Inverter
On certain models the polarity of the video signal can be set by the
invert switch so that, for instance, C band reception can be achieved.
After the invert selector switch this signal forms the BASEBAND input
to the Video Matrix.
7.3 PAL Deemphasis
The baseband signal is applied to the non-inverting input of an
amplifier which has a PAL pre-emphasis network in its negative
feedback loop. The output of this amplifier is a PAL de-emphasised
signal which is attenuated by 6dB to make it level compatible, and
forms the PAL input to the Video Matrix.
Atter the deemphasis the PAL signal is band limited by the SMHz Low-
Pass Filter, followed by a Group Delay Corrector to compensate for
distortions in the filter and ac coupled into the clamp to remove the
25Hz energy dispersal waveform. This signal is the NORMAL video
input to the Video Matrix.
7.4 Video Matrix
This is a cross wire matrix of switches which can select any one of the
Video sources and make it available to each of the three outputs. In
addition to the three sources described above video is also fed to the
matrix from AUX 1, AUX 2 and the Internal Decoder, each signal being
clamped to the same level to avoid switching disturbances . Note that
not all these signals are present on ail models.
Notall switching selections are made possible, forinstance BASEBAND
video can only be sent to AUX 1.
Output video from the matrix is sent to AUX 1, AUX2 and the Internal
Decoder. The black level on the Internal decoder video is preset to a
suitable level for it.
All Video Matrix, Invert and Video Gain are controlled via i2C Bus from
{C600.
Block Diagram OSD-Processor
cs
SCK
SIN
|
|
|
|
voor @)
ae
|:
°
vbbd2
STR 631 /STR 632
?C Bus
a
>
NO_SYNC
To 10600 { sas
&
OSD_csS
OsD_ScK
;
OSD_SDA
onune
OSD_RESET
To TV SCART
OSD Bus trom
and modulator
1600
Video Processing Block Diagram
7.5 OSD and Syne
The video to AUX 2is also used as the feed for the On Screen Display
(OSD) insertion circuit which is used to add Menus and Status
information for the Video to be displayed on the TV. The video to AUX
2 has its sync tips clamped at a predetermined level. The Sync
separator circuit uses Q404 to slice the video between sync tip and
black level and produce sync information at its collector. This signal is
inverted by Q403 to provide the negative going sync stream for the
OSD chip IC501. ©
:
In the presence of a valid sync signal C408 is charged enough to turn
on Q402 and signal the presence of valid sync to 1C200 via the
NO_SYNC signal. To further qualify the presence of sync D406, C452,
R457 form a peak sync detector to provide IC200 with the additional
PK_SYNC signal.
In the absence of valid sync IC501 is instructed to generate its own
sync so. that OSD can still be used.
Allcontrol of the OSD is viathe dedicated
4 wire OSD bus OSD_RESET,
OSD_CE, OSD_SCK, OSD_SDA.
The output from the OSD is used to drive the TV SCART and video
input to the Modulator.
HOR* VERT*
1 14.32MHz (NTSC)
| 17.73MHz (PAL)
Reading address.
control circuit
Blinking circuit
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