MSI P41T-C31 Bedienungsanleitung Seite 26

advance dRaM Configuration
Press <enter> to enter the sub-menu.
dRaM timing Mode
Selects whether dRaM timing is controlled by the SPd (Serial Presence de-
tect) eePRoM on the dRaM module. Setting to [auto] enables dRaM timings
and the following related items to be determined by BioS based on the con-
figurations on the SPd. Selecting [Manual] allows users to configure the dRaM
timings and the following related items manually.
CaS Latency (CL)
When the dRaM timing Mode sets to [Manual], the field is adjustable. this
controls the CaS latency, which determines the timing delay (in clock cycles)
before SdRaM starts a read command after receiving it.
tRCd
When the dRaM timing Mode sets to [Manual], the field is adjustable. When
dRaM is refreshed, both rows and columns are addressed separately. this
setup item allows you to determine the timing of the transition from RaS (row
address strobe) to CaS (column address strobe). the less the clock cycles, the
faster the dRaM performance.
tRP
When the dRaM timing Mode sets to [Manual], the field is adjustable. this
item controls the number of cycles for Row address Strobe (RaS) to be al-
lowed to precharge. if insufficient time is allowed for the RaS to accumulate its
charge before dRaM refresh, refreshing may be incomplete and dRaM may
fail to retain data. this item applies only when synchronous dRaM is installed
in the system.
tRaS
When the dRaM timing Mode sets to [Manual], the field is adjustable. this set-
ting determines the time RaS takes to read from and write to a memory cell.
tRtP
When the dRaM timing Mode sets to [Manual], the field is adjustable. time
interval between a read and a precharge command.
tRFC
When the dRaM timing Mode sets to [Manual], the field is adjustable. this set-
ting determines the time RFC takes to read from and write to a memory cell.
tWR
When the dRaM timing Mode is set to [Manual], the field is adjustable. it speci-
fies the amount of delay (in clock cycles) that must elapse after the completion
of a valid write operation, before an active bank can be precharged. this delay
is required to guarantee that data in the write buffers can be written to the
memory cells before precharge occurs.
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