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v
a1
B2
B3
Bb
Bs
BE
B87
7057 (SN74LS74)
Pin name
7055 (P8049)
To
1
[40}«
+50
gy
[33] 11
XTALI
|
[3s] 27
XTAL2
4]
[27] P26
RESET
s
[36] P25
6
[35] P26
[a] P17
[33] pis
32] Pts
$s
Fi Pre
INT
14
30]
P13
EA
rz
2s] P12
RD
13)
2] Pi
PSEN
[ie
[27] P10
is|
26}—«
+50
wr
6
[25] PROG.
ALE
7
24] P23
Bo B7
(BUS)
[|
[2a]. P22
fis]
[22] P21
[20]
[21] P20
P20 + P23
(PORT 2)
PROG
P10+P17
(PORT 1)
P247P26
P27
"1
3
8
TRUTH
TABLE
20
20
INPUTS
OUTPUTS
CLEAR
[CLOCK |PRESET
a
82
T
Sire. [ {Pree
1
x
H
H
L
H
a
w
[fr |
fa
L
(eT
7
H
L
H
H
Qo
Qo
18075 0 13
Don't care
= Transi
>) s a
Pin no
en ane
10
W
12+19
21424
25
27434
35+ 37
= Low voltage level (< 0.8 V)
High voltage level (2 2 V)
Function
Test input for mains interruption
Commends IC7055 to transfer data on clock time, tape deck
situation and counter displays from its internal RAM to the
external RAM (IC7053 and 1C7084).
6 MHz crystal input
Reset performs following functions, when it goes from
high to low (2 5 ms after To is low)
1 Sets programe counter to zero.
6 Sets Port 1 and 2 to
2. Sets stack pointer to zero
input mode
3 Select register bank 0
7. Disable interrupts
4 Select memory bank 0
8 Stops timer
5 Sets BUS to high impedance
9 Clears timer flag
state
10 Clears Fo and Fy
11. Disable To
Not used (single step)
Interrupt. Used to jump to a subroutine {every 128 ms depen
ding on P14)
External access memory
Read (active low), output strobe during a BUS read
Program store enable (active low). This output occurs only
during a fetch to external program memory (IC7058)
Write (active low). Output strobe during a BUS write.
Address latch enable. This signal occurs once during each cycle.
True bidirectional which can be written or read
synchronously, using the RD, WR strobes. The port can also be
statically latched
Contains the 8 low order program counter bits during an
external program memory fetch, and receives the addressed
instruction under the control of PSEN. Also contains the
address and data during an external RAM data store instruction,
under control of ALE, RD and WR
P20-P23 contain the four high order program counter bits
during an external program memory fetch and serve as a 4-bit
output expander bus for P8243. *
167061 on U20 or 17063 on Panel 20.
Output strobe for output expander P8243 1C7061 on U20 or
1C7063 on Panel 20.
{nput or output port P10-P13 output ports, P14 output port
to enable interrupt P15 = P17 input ports.
Output ports used for chip selection.
P24 if low external RAM (IC7053 and 1C7054) is selected.
P25 it high output expander P8243 (1C7061 on U20) is
selected, it low P8243 (1C7063 on Panel 20) is selected.
P26 Used for chip selection on Pane! 20
Not used.
Test input of tuning
ion from low to high level
The level of Q before the indicated input
conditions were established
54
7058 (P8355)
cf
U
to}—<+50
ce
[2
39]
PB7
CLK
[3
38}
PBB
RESET
[4
37)
PBS
consecteo
[5
36] PBL
READY
[6
35}
PBI
MEMORY
{7
34]
PB2
ror
[8
33] Pat
RO
[9
32]
PBO
Tow
[10
31]
PAZ
ALE
[11
30)
PAS
so [12]
29] PAS
Bi
13,
28}
PAL
B2
|
27)
PAZ
B3
LIS.
26}
PAZ
BL
[16
25)
PAL
BS
{17
24)
PAO
BS
[8
23]
A10
a7
fig
[22] as
ok
21} as
14
U
6}
+50
2
15] O19
3
He]
09
G
[13] 0,
7
[12] 9
6
Ti] MR
[7|
10] oF
oc)
3] %
7062 (HEF 4040)
Pin name
Pin no
Function
cE
1
Active low
ce
2
Chip enable input. If active high, this chip is selected.
CLK
3
Not used
RESET
4
An input high on reset causes all pins in ports A and B to
assume input mode
N.C.
5
Not internal connected
READY
6
Not used
MEMORY
7
Active low
1oR
8
Input output read. When pin 2 is high, a low on IOR will
output the selected I/O port onto the BUS.
RD
9
READ. If the latched CE is high when read goes low, data
from the selected ROM location go to the BUS,
tow
10
Input output, write. If the latched CE is high, a low on JOW
causes the output port pointed to be the latched value of BO to be
written with the data on BUS 0°
ALE
"
Address latch enable. When ALE is high BO-7, A8-10 and CE
enter address latched. These signals are latched in the trailing
edge of ALE.
8087
12719
Bi-directional Address/Data bus.
ABTAIO
= 21423
These are the high order bits of the ROM address
PAQ=3,7
24=27,31
Input port
PAG=6
28+ 30
Output port
PBO,1,3,6 — 32,33,35,38_ Input port
PB2,7
34,39
Output port
SEE P21-a AND P21-b FOR P8243 (7061)
7064 (SN74LSOON)
oe
FIOAPAR
A
U
1A
1
14 }—e+5a
9
ee ee
'0
és
18
2
13]
4A
9,
f
{
ir =
otek
1c
3
12]
6B
a
es
|
2a
[k
ii] 4c
28
Remark:
5}
10]
34
A high on MR (master reset input point 11) clears all
2c
[6
3]
36
counter stages and forces all outputs low, independent
of CP (clock pulse point 10)
7
4] ac
Qp to 014 are fully buffered outputs
<7
Op to CP:2, 4 is CP:4, 07 is CP:8
See also pulse diagram
Low voltage level < 1,5 V - high voitage level > 3 V
INPUT
OUTPUT
A
B
c
L
L
H
L
H
H
H
L
H
H
q
[i
L_ = Low voltage level (<0,8 V)
H = High voltage level (> 2 V)
18076 013
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