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Description
9. Integrated Peripherals
- two UARTs to interface remote control receivers, DVD front end,
modem ...,
- one I
2
C controller to interface serial memories, remote control
receivers, microcontrollers...,
- 2 SmartCard interfaces (ISO7816-3) for DVB-DSS conditionnal
access, pay per view ...,
- PWM/timer module for control of system clock,
- 34 programmable I/O pins,
- OS Link interface,
- JTAG with boundary scan for debug.
• Functional Modules
1. CPU
The Central Processing Unit (CPU) on the STi5505 is the ST20-C2 32-
bit processor core. It contains instruction processing logic, instruction
and data pointers and an operand register. It directly accesses the high
speed on-chip SRAM memory, which can store data or programs, and
uses the Caches to reduce access time to off chip program and data
memory.
The processor can access memory via the general purpose External
Memory Interface (EMI) or via the SDRAM EMI which is shared with the
MPEG decoder.
2. Memory Subsystem
The on-chip SRAM memory system provides 160 Mbytes/s internal
data bandwidth, supporting pipelined 2 cycles internal memory access
at 25ns cycle times. The memory system consists of 2 Kbytes of
SRAM, 2Kbytes of instruction cache, a 2Kbytes data cache that can be
programmed to be SRAM, and an external memory interface (EMI).
The STi5505 product has 2 Kbytes of on-chip SRAM. The advantage
of this is the ability to store time critical code on chip, for instance
interrupt routines, software kernels or device drivers, and even frequently
used data without these being flushed from the caches.
The instruction and data caches are direct mapped with a write-back
system for the data cache and support burst accesses to the external
memories for refill and write-back which are effective for increasing
performance with page-mode and SDRAM memories.
The STi5505 EMI controls access to the external memory and
peripherals while the SDRAM EMI provides access to the SDRAM
buffer for the MPEG decoders, ST20 and DMA peripherals.
The STi5505 EMI can access a 16 Mbytes (or greater if DRAM is used)
physical address space in each of the four general purpose memory
banks, and provides sustained transfer rates of up to 80 Mbytes/s.
Peripherals that support an asynchronous data acknowledge are
supported as is an external Power PC which can share the bus with the
STi5505 and access the SDRAM buffer through the device.
High memory bandwidths up to 200 Mbytes/s can be supported by the
SDRAM EMI.
The internal memory interconnect provides buffering and arbitration of
memory access requests to sustain very high throughput of memory
accesses.
3. System Services Module
The system services module includes :
- Phase locked loop (PLL) - accepts 27MHz input and generates all
the internal high frequency clocks needed for the CPU and the OS-
Link.
- test access port - JTAG compatible.
- Diagnostics controller accessed via the JTAG port providing :
- Bootstrapping during development
- Hardware breakpoint and watchpoint
- Real time trace
- External LSA triggering support.
4. Serial Communications
To facilitate the connection of this system the front end device and
other peripherals, two UARTs (ASCs) are included in the device. The
UARTs provide an asynchronous serial interface.
The UART can be programmed to support a range of baud rates and
data formats, for example, data size, stop bits and parity. Two
synchronous serial communications (SSC) interfaces are provided on
the device. These can be used for a remote control device for example
via an I
C or SPI bus.
2
5. Interrupt Subsystem
The STi5505 interrupt subsystem supports eight prioritized interrupt
levels. Two external interrupt pins are provided. Level assignment
logic allows any of the internal or external interrupts to be assigned
and, if necessary, share any interrupt level.
2 - 12
6. Front End Interface & DVD Decryption
The front end interface accepts sectors in the case of DVD, MPEG-1
system stream in the case of VCD and PCM data for CD-DA applications
on an I
2
S interface. In the case of VCD and CD-DA disks the subcode
information is input via a simple asynchronous serial interface similar
to a UART.
The bitstream and subcode stream then pass through a "sector
processor" block which handles sector filtering in the case of DVD and
sectorizing using the subcode stream for VCD and CD-DA systems.
The block also handles overspeed processing for all systems. The
capturing of CD-DA sectors is based on a flywheel tiner to improve
robusters by concealing erros in the subcode stream. For DVD the
data, having had sector headers removed, then passes through a DVD
conformant decryption stage and is written into any of the system
memories using a programmable DMA engine. When a subcode
stream is present it is locally buffered, by subcode block and can be
read by the CPU for subsequent processing, if required.
7. PWM and counter module
This unit includes three separate pulse width modulator (PWM)
generators using a shared counter, and three timer compare and
capture channels sharing a second counter.
The counters can be clocked from a prescaled internal clock or from a
prescaled external clock via the capture clock input and the event on
which the timer value is captured is also programmable.
The PWM counters are 8-bit with 8-bit registers to set the output high
time. The capture/compare counter and the compare and capture
registers are 32-bit.
8. Parallel Programmable IO module
40 bits of parallel I/O are provided. 34 of then are connected to actual
PIO pins. Each bit is programmable as an output or an input. The output
can be configured as a totem pole or open drain driver. Input compare
logic is provided which can generate an interrupt on any change on any
input bit.
Many pins of the STi5505 device are multifunction and can either be
configured as PIO or connected to an internal peripheral signal.
9. MPEG Video decoder
The video decoder is a real-time video compression processor
supporting the MPEG-1 and MPEG-2 standards at video rates up to
720 x 480 x 60 Hz and 720 x 576 x 50 Hz. Picture format conversion
for display is performed by vertical and horizontal filters. User-defined
bitmaps may be superimposed on the display picture through use of
the on-screen display function.
10. PAL/NTSC encoder
The digital encoder which is integrated in the STi5505 converts a
multiplexed 4:2:2 YUV stream into a standard analog baseband PAL/
NTSC signal and into RGB analog components. The encoder can also
perform closed-caption, CGMS or teletext encoding and allows
Macrovision TM 7.01/6.1 copy protection.
11. MPEG-2 Audio / Dolby AC-3 Decoder
The audio decoder is a Dolby AC-3 decoder capable of decoding both
5.1 and 2 channel DVD comformant bitstreams. The decoder also
handles MPEG-1 (layers 1 & 2) and MPEG-2 layer 2 (6 channels).
Downmix to 2 channels is possible for Dolby and MPEG standards with
optional pro-logic encoding.
The decoder directly accepts MPEG-2 PES streams as input. The
decoder is capable of supporting IEC6958-IEC61937 formatted outputs
for AC-3 and MPEG audio, linear PCM (left & right,16, 18, 20 & 24 bits),
zero output (Mute mode) and PCM audio.
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