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7XV5662-0AD00
The timeslot 16 is provided for signalling. Frame 0 (Multiframe Alignment Signal) of a
multiframe includes the Y–bit which is set to "1" in the case of Loss of MFAS (Loss of
Multiframe Alignment Signal).
Bit No.
In the subsequent 15 frames (1 to 15) of the multiframe the bits 1 to 8 are set to "1".
In T1 mode the D4 and ESF frame structure is supported.
The ESF frame structure consists of 24 frames with 193 bits each. The first bit of any frame
is reserved for synchronisation and error indication. The assignment is shown in the
following table. The FAS bits are reserved for synchronisation, and the DL bits form a data
link via which alarms are transmitted. If the synchronisation is lost, the bit pattern
"1111111100000000" is transmitted via the DL bits. A CRC–6 is generated via the user data
and transmitted accordingly. There will be no evaluation or external signalling of the CRC
through the CC–2M.
Multi–frame No.
C53000-B1174-C205-1
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1
2
0
0
Multi–frame Bit No.
1
0
2
193
3
386
4
579
5
772
6
965
7
1158
8
1351
9
1544
10
1737
11
1930
12
2123
13
2316
14
2509
15
2702
16
2895
17
3088
18
3281
19
3474
20
3667
21
3860
manuals search engine
3
4
5
0
0
1
FAS
–
–
–
0
–
–
–
0
–
–
–
1
–
–
–
0
–
–
–
1
–
English
6
7
8
Y
1
1
DL
CRC
M
–
–
C1
M
–
–
–
M
–
–
C2
M
–
–
–
M
–
–
C3
M
–
–
–
M
–
–
C4
M
–
–
–
M
–
–
C5
M
–
–
–
M
–
43
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