Inhaltsverzeichnis
Werbung
8
Belegungsplan Leiterplatte CPU
B1
#FD1
1
C232
R85
C209
L80
L29
C245
C235
V14
L25
L42
C242
R78
C252
C237
C187
C240
C241
R77
L31
C193
L20
N2
C192
L34
C194
L21
C198 C200
C73
C202
L37
C16
L38
C14
B5
R107
C243
C239
R22
#FD3
1
X1
Bild 25
Belegungsplan LP CPU X4.3
C116
R116
C179
C157
C175
C155
T
R
P
N
M
L
K
D3
D2
J
H
G
F
E
D
C
B
A
1
2
3
7
8
C169
C153
25 4
2
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2
AE
AD
AC
AB
AA
Y
W
V
U
T
R160
R
L28
P
D1
R123
N
M
C293
R125
L
L24
R163
K
J
H
R213
G
C335
F
R215
E
C342
D
C
B
R219
A
R220
H6
H5
H4
25
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2
R29
C339
2
G2
3
2
1
G6
L93
3
4
L14
C181
C182
C230
R567
C180
U3
TOP8
TOP7
TOP9
C327
TOP5
TOP11
TOP12
D13
R119
R120
TOP6
C214
C196
C216
C5
C283
C208
C217
R1
C1
C4
C285
C3
TOP3
L92
L91
C234
C324
C321
R11
R
3
R
2
R21
R33
L33
C72
TOP2
R122
TOP26
C289
N6
L63
E1
B4
CON7
B2
TOP10
R117
R71
R150
C296
R151
C269
R152
C262 C266
R140 R142
C163
C290 C295
R158
T
R
P
N
L26
M
L
K
J
H
L85
G
R55
F
R54
E
L66
D
C
L73
B
A
R47
L83
R48
R72
L84
9
1
2
3
7
8
9
C301
L39
V23
L36
1
AE
L43
AD
AC
AB
L48
AA
Y
C222
R96
W
V
L49
U
T
R
R280
L50
P
D5
U8
N
C280
M
R136
L
K
R121
C276
J
H
G
C279
R102
F
R
1
1
1
R
9
7
E
D
C
C278
R134
B
R172
A
C300
C322
1
R171
R254
R303
1
C323
R255
C264
4
L72
L30
R253
C113
TOP17
C347
L1
TOP23
L68
TOP18
C346
L3
R247
TOP24
L67
R245
TOP19
C345
L6
TOP16
C350
L18
TOP20
C312
L9
TOP15
C349
L17
R566
TOP21
C311
L10
TOP13
C309
R13
L15
TOP22
C310
L12
TOP14
C271
L16
L90
TOP25
L87
C267
R84
L2
D14
V24
V17
1
R141
C9
R59 R60
R68
R89
V25
D15
L4
TOP4
1
R169
C185
R87 R88
R70
R25
V3
V19
C8
+
R37
L32
TOP1
V12
C6
L35
+
R168
C15
C27
+
V10
C26
V9
L7
L8
R170
L11
V21
C205
C28
L23
L22
B3
2
V13
1
1
#FD2
Messpunkte an CON9:
GND
+24V
+V
(+24V)
MOT
Messpunkte auf der Leiterplatte:
TOP2
+24V
TOP3
+5V
TOP25 +24V TPH
TOP26 +V
(+24V)
MOT
LED auf der Leiterplatte
H1
+3,3V
H7
LED FPGA
während
Bootvorgang an,
danach blinkend
29
Werbung
Inhaltsverzeichnis
