Tabelle 1 Pinbelegung X100 - Sys Tec Electronic ECUcore-EP3C Bedienungsanleitung

Development Board ECUcore-EP3C
IO5 FPGA-Pin L1
4
5 GND
IO8 FPGA-Pin K5
6
7 IO10 FPGA-Pin R1
8 IO12 FPGA-Pin P1
9 IO13 FPGA-Pin N3
10 IO15 FPGA-Pin N12
GND
11
12 IO18 FPGA-Pin P16
IO20 FPGA-Pin N16
13
14 IO22 FPGA-Pin L13
15 /MR Reset-IC /MR
+3V3
16
Pin Name
C
1 TDI
2 GND
3 TMS
4 Hex-MRST
Hex-PL
5
6 Err-LED
Run-LED
7
8 GND
9 +2V5_Eth0
Eth0_Rx-
10
11 Eth0_Rx+
Eth1_Link
12
13 GND
14 Eth1_Rx-
Eth1_Rx+
15
16 +3V3
Tabelle 1 Pinbelegung X100
Der Name der IO-Pins kommt von der ursprünglichen Verwendung
als stand-alone POWERLINK-Node.
6
4
5
6
7
8
9
10
11
12
13
14
15
16
Anschluss
FPGA-TDI
FPGA-TMS
FPGA Pin N11
FPGA Pin T14
FPGA Pin F14
FPGA Pin C11
PHY0-VDDRCV
PHY0 Rx-
PHY0 Rx+
PHY1 LED0
PHY1 Rx-
PHY1 Rx+
IO6 FPGA-Pin N2
IO7 FPGA-Pin N1
IO9 FPGA-Pin L4
IO11 FPGA-Pin P2
GND
IO14 FPGA-Pin T15
IO16 FPGA-Pin N14
IO17 FPGA-Pin P15
IO19 FPGA-Pin R16
IO21 FPGA-Pin N15
GND
IO23 FPGA-Pin L16
GND
Pin Name
D
1 TDO
2 TCK
3 RxD0
4 TxD0
GND
5
6 Hex-CLK
Eth0_Link
7
8 Eth0_Speed PHY0 LED1
9 Eth0_Tx-
Eth0_Tx+
10
11 GND
Eth1_Speed PHY1 LED1
12
13 +2V5_Eth1
14 Eth1_Tx-
Eth1_Tx+
15
16 GND
© SYS TEC electronic GmbH 2011 L-1266d_02
Anschluss
FPGA-TDO
FPGA-TCK
FPGA-Pin G2
FPGA Pin G1
FPGA Pin M10
PHY0 LED0
PHY0 Tx-
PHY0 Tx+
PHY1 VDDRCV
PHY1 Tx-
PHY1 Tx+