Inhaltsverzeichnis
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1
2
wake up
GND
JP101
uC clock
A
MUST be 12MHz for internal BOOT ROM and USB
R109 33R
C100
XIN
18pF
XT100
R112
GND
12 MHz
GND
1M
C101
XOUT
18pF
R118 33R
C102
XIN32
12pF
XT101
R120
GND
32.768KHz
1M
C103
XOUT32
12pF
C104
PLLRCA
100nF
R122 300R
C105
1nF
R125
1M
GND
Reset
B
3V3
3V3
C106
GND
U101
100nF
TPS3838K33DBVT
R136
10k
1
Reset
CT
4
RST
2
1
GND
3
MR
C107
3
470p
PB100
GND
GND
R135
Bypass (default)
0R
uC Power
3V3dly
TP103
C
3V3 DELAY
3,3V delayed
Delay = 133 usec
R132
S
D
3V3
D
S
3V3dly
0R
C123
100nF
Q100
SI2333
1V2uC
R131
1M
GND
1V2uC
1V2uC
C120
GND
100nF
1V2uC
VddBU
C121
R139
GND
100nF
C122
0R
GND
100nF
3V3dly
C124
GND
1V2bat
100nF
D
1V2uC
C135
GND
100nF
3V3a
1V2bat from I/O sheet, I2C-RTC's coin cell
R139+C122 optionally form a lowpass for delaying the VddBU-Reset Cell.
This will -not- work with VddBU coming from a coin cell (JP100 pos 2-3).
1
2
3
VddBU
VddBU
1M to reduce bat current in SHDN mode
R100
R101
TP100
TP101
1M
1M
TP
TP
WakeUp
SHDN
Board sleep mode not supported
U100B
163
162
WKUP0
SHDN
JTAG
202
1
XIN
TRST
2
TDI
6
TMS
8
TCK
203
4
XOUT
TDO
R115 1k
158
164
XIN32
JTAGSEL
VddBU
Note 1
R119 1k
165
TST
VddBU
Note 1
R121 1k
159
104
XOUT32
BMS
GND
JP104
207
14
PLLRCA
RST
GRIDARM-208
JTAGSEL:
high for Boundary Scan
(has int. 100k pulldown)
BMS:
low for external BOOT via CS0
(SPI-flash or 16bit wide NOR flash)
(has int. 100k pullup)
Note 1:
3V3
In harsh environments it is strongly
recommended to tie this pin to GNDBU
if unused or to add an external lowvalue
resistor (such as 1 kOhm).
R134
2k2
uC-Reset
GND
TP102
TP
Reset uC
U100A
12
10
VDDIO
GND
30
24
VDDIO
GND
44
37
VDDIO
GND
55
38
VDDIO
GND
68
50
VDDIO
GND
77
56
VDDIO
GND
GND
94
65
VDDIO
GND
107
66
VDDIO
GND
120
79
VDDIO
GND
137
88
VDDIO
GND
151
100
VDDIO
GND
177
106
VDDIO
GND
198
114
VDDIO
GND
124
GND
3V3dly
22
135
VDDCORE
GND
36
140
VDDCORE
GND
76
146
VDDCORE
GND
96
175
VDDCORE
GND
110
179
VDDCORE
GND
144
193
VDDCORE
GND
183
195
VDDCORE
GND
194
VDDCORE
1V2uC
204
201
VDDOSC
GNDOSC
157
160
VDDOSC32
GNDOSC32
161
166
VDDBU
GNDBU
205
206
VDDPLLA
GNDPLLA
208
GNDPLLA
3V3dly
199
200
VDDPLLB
GNDPLLB
GND
173
174
AVDD
AGND
GNDa
GRIDARM-208
3
4
5
3V3
GND
R137
JTAG
0R
3V3
J101
SHF-105-01-L-D-TH
alternative socket
R126
0R
TRST
R107
100R
TDI
RTCK
R108
100R
TMS
TDI
R110
100R
TCK
TDO
R111
100R
TDO
TMS
R113
100R
RTCK
TCK
R114
100R
3V3
JTAG
R116
R117
R138
10k
10k
GND
0R
GND
GND
GND
R133
0R
R123
R124
10k
100R
current consumption CPU,
worst case:
3,3V: 36mA
1,2V: 100mA
R127
GNDa
0R
L101
3V3a
BLM21P331SN1D
C111
100nF
GND
C112
C113
C114
C115
C116
C117
C118
100nF
100nF
100nF
100nF
100nF
100nF
100nF
GND
C125
C126
C127
C128
C129
C130
C131
C132
C133
C134
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
GND
4
5
6
IO
IO.SchDoc
CAN_Tx
CAN_Rx
Dbg_TxDi
Dbg_RxDi
Term_TxDi
Term_RxDi
Term_RtSi
J100
uC-Reset
Term_CtSi
10
9
8
Memory
7
6
Memory.SchDoc
5
4
3
2
1
CON2X5_S
uC-Reset
1GB-Ethernet
1GB-Ethernet.SchDoc
uC-Reset
uC-Reset
Reserved uC pins
U100D
19
Reserved
21
Reserved
23
Reserved
25
Reserved
60
Reserved
62
Reserved
64
Reserved
69
Reserved
71
Reserved
73
Reserved
75
Reserved
95
Reserved
97
Reserved
111
Reserved
113
Reserved
123
Reserved
139
Reserved
141
Reserved
142
Reserved
143
Reserved
145
Reserved
147
Reserved
150
Reserved
GND
GRIDARM-208
6
7
8
Serial
Serial.SchDoc
CAN_Tx
CAN_Rx
Dbg_TxDi
Dbg_RxDi
Term_TxDi
A
Term_RxDi
Term_RtSi
Term_CtSi
PowerSupply
PowerSupply.SchDoc
B
M100
6 Layer Stack
Marking for Copper Layers
C
M101
M102
AP M3
AP M3
M103
M104
AP M3
AP M3
D
C PEAK-System Technik GmbH
Title:
PEAK-gridARM-EVB
Sheet:
uController
PEAK-System Technik GmbH
Otto-Röhm-Str. 69
Customer:
Version:
1.2
D-64293 Darmstadt
Variant:
*
Engineer:
StS
*
Date:
30.05.2012
File:
uController.SchDoc
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