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Verfügbare Sprachen
Verfügbare Sprachen
A reliable shifting is proceeded under the follo-
wing circumstances:
- The external sync input must have had a va-
lid sync signal for a short time. This time
span is needed to detect the external fre-
quency and prepare the internal oscillator.
- The external frequncy mustbe in a range of
+/- 200 Hz around the internal fixed frequen-
cies.
HINT:
The internal frequeny which is generated in ca-
se of a droped external sync is not identical to
the external frequency in terms of a VCXO - but
similar !
It is one of the fixed frequencies of the internal
oscillator.
KEY-LOCK
To avoid unwanted operation, the SELECT but-
ton may be locked.
Pushing the button for more than 2 seconds will
activate / deactivate the Key-Lock function. The
activated state is displayed by the KEY-LOCK
LED.
THE CLOCK OUTPUTS
EUCG V51 Mk II generates multiple of signals
(see connection diagram on page 8).
When V51 Mk II is mounted to DIGI RACK 503/
04/06 these signals are distributed to the inter-
nal bus system.
V52, V54 and V58 units connected to the bus
will be supplied synchroneously.
256 Fs is 256 times the single clock infor- ma-
tion. It is also known as master-clock
(MCLK) and serves mainly to drive
modulators of A/D converters. Its Fre-
quency relative to 48 kHz is 12.288
Mhz.
128 Fs is 128 times the single clock infor- ma-
tion. It serves mainly to drive AES
transmitters but is also used in SRC´s
and A/D converters. Its Frequency re-
lative to 48 kHz is 6.144 Mhz.
64 Fs
is 64 times the single clock infor- mati-
on. It is also known as bit-clock
(BCLK) or serial clock (SCLK) and
serves mainly to create the digital da-
taword. Its Frequency relative to 48
kHz is 3.072 Mhz
Fs
is the single clock information. It is al-
so known as left-right-clock (LRCLK)
and serves to indentify left and right
information inside the digital data-
word. Its Frequency is 48 kHz.
ERR
is an error information and serves for
muting, locking, calibration etc. on the
connected modules.
TCBL
is theso called blockstart information
and is used to synchronise the output
words from ADC´s and SRC´s
WCLK
is identical toFs (see above)
AES-Sync is the AES/EBU sync signal which is
generated out of an external or inter-
nal clock source. It is balanced accor-
ding to AES 3/11 recommendations
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