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2. CARTRIDGE CONNECTORS
Pin
Pin
Pin
1
3
5
7
K]
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
ai
43
45
47
49
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17-32
28
49
50
vo
Name
cs
0
o
cS12
Reserve
=
WAIT
1
o
MI
o
IORQ
WR
o
0
RESET
o
A9
o
A11
o
A7
o
A12
o
A14
o
A1
o
A3
o
A5
vo
Dt
vo
D3
vo
D5
vo
D7
-
GND
-
GND
-
+5V
-
+5V
SOUNDIN
1
Name
Content
csi
ROM
cs2
ROM
cs12
ROM
SLTSL
Slot
Reserve
Reserved
RFSH
Refresh cycle signal
CPU's
WAIT
INT
Interrupt
Mi
Signal expressing
This signal controls direction
BUSDIR
Cartridges
cartridge
5
IORG
VO
MERG
Memory
WR
Write timing
RD
Read
RESET
System
Reserve
Reserved
-
Address
A0
A15
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
addresses
4000
- 7FFF
addresses
8000
—
addresses
4000
-BFFF
select signal
line
use
signal
—
WAIT
request signal
signal
request
fetch cycle
CPU
are
selected and
at
data transmission time
signal
request
request signal
signal
timing
signal
signal
reset
line
use
signal
—
bus
signals
1
2
Name
€82
SLTSL
RFSH
INT
BUSDIR
MERQ
RD
Reserve
A15
A10
A6
A8
A13
AO
A2
A4
DO
D2
D4
D6
CLOCK
Swi
sw2
+12V
—12V
select
signal
select signal
BFFF
select
signal
(for 256k
inhibited
to
CPU
external data bus buffer
of
is
level
output
from
L
inhibited
vo
o
0
o
ï
1
o
0
-
o
o
o
o
o
o
o
o
vo
vo
vo
vo
[e]
-
-
-
-
ROM)
each
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