Grundig UMS 15 Servicehandbuch Seite 15

UMS 15
IC601 LA9240ML (Servo Signal Processor)
Vcc1 LDS LDD BH1 PH1 LF2 VR REF1 Vcc2 FSS
64 63 62 61 60 59 58 57 56 55
APC REF
RF DET
FIN2 1
VCA
2
FIN1
I/V
E 3
µ-com
BAL VCA
INTER FACE
4
F
TB 5
TE
TE- 6
TE 7
TESI 8
T.SERVO & T.LOGICK
SCI 9
10
TH
11
TA
TD- 12
SPINDLE SERVO
13 F.SERVO & F.LOGICK
TD
JP 14
TO 15
FD 16
17 18 19 20 21 22 23 24 25 26
FD- FA FA- FE FE- AGND SP SPI SPG SP-
IC603 LA6541 (Pick-up Actuator & Motor Driver)
Vcc Vref VIN4 VG4 Vo8 Vo7 GND Vo6
24 23 22 21 20 19 18
Vcc
11k
Level BTL
Sift Driver
Level BTL
Sift Driver
11k
1 2 3 4 5 6 7
Vcc Mute VIN1 VG1 Vo1 Vo2 GND Vo3
GRUNDIG Service
Platinenabbildungen und Schaltpläne / Layout of PCBs and Circuit Diagrams
DRF CE DAT CL CLK DEF
54 53 52 51 50 49
48 NC
TBC
47
46 FSC
45 DGND
44 SLI
SLC
43 SLC
42 RFS-
RF Amp
41 RFSM
40 CV+
CV-
39
38 SLOF
37 HFL
36 TES
TOFF
35
34 TGL
33 JP+
SLED SERVO
27 28 29 30 31 32
SPD SLEQ SLD SL- SL+ JP-
Vo5 VG3 VIN3 CD RES
17 16 15 14 13
11k
BTL Level
RESET
Driver Sift
BTL
Level
Driver Regulator
Sift
11k
8 9 10 11 12
Vo4 VG2 VIN2 Reg OUT Reg IN
UMS 15
IC602 LC78622E (Digital Signal Processor)
Pin Name I/O Function
1 DEFI I Input terminal for detect signal of defect
2 TAI I Input terminal for test.
3 PDO O The phase comparison output terminal for external VCO control.
4 VVSS – Ground terminal for built-in VCO
5 ISET I Resistance connection terminal for electric current adjustment of PDO output.
6 VVDD – Built-in VCO power supply terminal.
7 FR I VCO frequency range adjustment.
8 VSS – Ground for Digital
9 EFMO O EFM signal output terminal for slice level control.
10 EFMIN I EFM signal input terminal for slice level control.
11 TEST2 I TEST pin. Normal time is non connection.
12 CLV+ O Output terminal for Disc motor control.
13 CLV- O Output terminal for Disc motor control.
14 V/P O Change of rough servo / phase control Rough servo : "H", Phase control : "L"
15 HFL I Input terminal of track search signal.
16 TES I Input terminal of tracking error signal.
17 TOFF O Output terminal of tracking off.
18 TGL O Output terminal for change of tracking gain.
19 JP+ O Output terminal for tracking jump control.
20 JP- O Output terminal for tracking jump control.
21 PCK O Clock monitor output terminal for EFM data playback. (4.3218 MHz)
22 FSEQ O Output terminal for detect of SYNC signal.
23 DVDD – +5V
24 CONT1 I/O
25 CONT2 I/O This output can control at serial control from
26 CONT3 I/O micro processor.
27 CONT4 I/O
28 CONT5 I/O
29 EMPH O Output terminal of de-emphasis monitor. "H" : de-emphasis
30 C2F O Output terminal of C2 flag
31 DOUT O Output terminal of digital out
32 TEST3 I Test pin.
33 TEST4 I Test pin.
EFMO VV VV PDO ISET FR
DD SS
9 6 4 3 5
1
Slice level
DEFI VCO Clock Oscillator
Control
& Clock Control
EFMIN 10
Syncrnous Detect
22
FSEQ
EFM Demodulation
12
CLV+
CLV
Digital Servo
13
CLV-
14
V/P
PW 49
SBCK 51 Subcode Dxract
47 QCRC
SBSY
SFSY 50
63
CS
53 µCOM
WRQ
Inter Fase
SQOUT 55
CQCK 57
COIN 56
General Ports
Servo Commander
RWC 54
15 16 17 20 19 58 18 24 25 26 27 28
HFL TES TOFF JP- JP+ RES TGL CONT1 CONT3
CONT2 CONT4
3 - 3 GRUNDIG Service
Platinenabbildungen und Schaltpläne / Layout of PCBs and Circuit Diagrams
Pin Name I/O Function
34 NC – Non connection.
35 MUTEL O Mute output terminal for L-ch
36 LVDD – Power supply for L-ch
37 LCHO O Output terminal for L-ch
38 LVSS – GND for L-ch
39 RVSS – GND for R-ch
40 RCHO O Output terminal for R-ch
41 RVDD – Power supply for R-ch
42 MUTER O Mute output terminal for R-ch
43 XVDD – Power supply of crystal oscillation
44 XOUT O Connection terminal of crystal oscillation (16.9344MHz)
45 XIN I Connection terminal of crystal oscillation (16.9344MHz)
46 XVSS – GND of crystal oscillation
47 SBSY O Output terminal for synchronizing signal of sub-cord block
48 EFLG O Output terminal for correction monitor of C1, C2, Single and Double
49 PW O Output terminal for sub-cord of P, Q, R, S, T, U and W
50 SFSY O Output terminal for synchronizing signal of sub-cord frame
51 SBCK I Input terminal for readout clock of sub-cord
52 FSX O Output terminal of Synchronizing signal (7.35kHz)
53 WRQ O Output terminal for standby of sub-cord Q output
54 RWC I Input terminal of read / write control
55 SQOUT O Output terminal of sub-cord Q
56 COIN I Input terminal of command from micro processor
57 CQCK I Clock input for reading sub-cord from SQOUT
58 RES I Reset (turn on : L)
59 TST11 O Test pin
60 16M O 16.9344MHz
61 4.2M O 4.2336MHz
62 TEST5 I Test pin
63 CS I Chip select terminal
64 TEST1 I Test pin
TEST2 TEST4
TST11
PCK TAI TEST1 TEST3 TEST5 V V
DD SS
7 21 2 59 64 11 32 33 62 23 8
2K ~8bit RAM Address
RAM Generatorl
Interpolalation Mute
Billingual
C1 C2 Error Detect &
Correct Control Flag
Digital Attenuator
Quadruple Over Sampling
Digital Filter
1bit DAC
L.P.F
X'tal Root
Timing Generator
29 48 60 61 46 52 45 44 43 39 41 42 40 37
CONT5 EMPH EFLG 16M 4.2M FSX XIN XV DD RV DD RCHO LCHO MUTEL
XV XOUT RV MUTER
SS SS
30 C2F
Digital Out
31 DOUT
34 (NC)
35 38 36
LV DD
LV SS
3 - 4