Inhaltsverzeichnis
Werbung
Prozessor / Processor:
Bus I/O
SDR_A[14..0]
RN1
1
SDR_A13
2
SDR_A12
3
SDR_A11
4
RN2
SDR_A9
1
SDR_A8
2
SDR_A6
3
SDR_A5
4
RN3
SDR_A14
1
SDR_A4
2
SDR_A2
3
SDR_A1
4
RN4
SDR_A0
1
SDR_A3
2
SDR_A7
3
SDR_A10
4
SDR_CLK
R79
SDR_DQMHH
RN5
1
SDR_CAS
2
SDR_CS
3
SDR_RAS
4
SDR_WE
RN6
1
SDR_CKE
2
SDR_DQMHL
3
SDR_DQMLH
4
SDR_DQMLL
SDR_DQ[31:0]
SDR_DQ31
SDR_DQ30
SDR_DQ29
SDR_DQ28
SDR_DQ27
SDR_DQ26
SDR_DQ25
SDR_DQ24
SDR_DQ23
SDR_DQ22
SDR_DQ21
SDR_DQ20
SDR_DQ19
SDR_DQ18
SDR_DQ17
SDR_DQ16
SDR_DQ15
SDR_DQ14
S
SDR_DQ12
SDR_DQ11
SDR_DQ10
SDR_DQ9
SDR_DQ8
SDR_DQ7
SDR_DQ6
SDR_DQ5
SDR_DQ4
SDR_DQ3
SDR_DQ2
8
RSDR_A13
SDR_DQ1
7
RSDR_A12
SDR_DQ0
6
RSDR_A11
5
10 ohm ARRAY 5% 1608X4
RSDR_A[14:0]
RSDR_A14
RSDR_A9
RSDR_A13
8
RSDR_A8
7
RSDR_A6
RSDR_A12
6
RSDR_A5
RSDR_A11
5
10 ohm ARRAY 5% 1608X4
RSDR_A10
RSDR_A9
RSDR_A14
RSDR_A8
8
RSDR_A4
RSDR_A7
7
RSDR_A2
RSDR_A6
6
RSDR_A1
RSDR_A5
5
10 ohm ARRAY 5% 1608X4
RSDR_A4
RSDR_A3
RSDR_A0
RSDR_A2
8
RSDR_A3
RSDR_A1
7
RSDR_A7
RSDR_A0
6
RSDR_A10
5
10 ohm ARRAY 5% 1608X4
BD2
60 ohm 200mA 1005
10 ohm 5% 1005
R_SDR_DQMHH
R_SDR_CS
R_SDR_RAS
R_SDR_CAS
R_SDR_WE
R_SDR_CKE
R_SDR_CAS
R_SDR_DQMHH
8
R_SDR_CS
R_SDR_DQMHL
7
R_SDR_RAS
R_SDR_DQMLH
6
R_SDR_WE
R_SDR_DQMLL
5
10 ohm ARRAY 5% 1608X4
R_SDR_CKE
8
R_SDR_DQMHL
7
R_SDR_DQMLH
6
R_SDR_DQMLL
5
10 ohm ARRAY 5% 1608X4
U4B
J2
ARM_D15
W10
J1
SDR_DQ31
ARM_D14
(MSB)
R10
J6
SDR_DQ30
ARM_D13
P10
K1
SDR_DQ29
ARM_D12
P11
K2
SDR_DQ28
ARM_D11
N12
K3
SDR_DQ27
ARM_D10
U11
J7
SDR_DQ26
ARM_D9
V11
K5
SDR_DQ25
ARM_D8
W11
J8
SDR_DQ24
ARM_D7
R11
L1
SDR_DQ23
ARM_D6
P12
L2
SDR_DQ22
ARM_D5
U12
L3
SDR_DQ21
ARM_D4
V12
K6
SDR_DQ20
ARM_D3
W12
M1
SDR_DQ19
ARM_D2
N13
M2
SDR_DQ18
ARM_D1
W13
L6
SDR_DQ17
ARM_D0
V13
SDR_DQ16
U13
SDR_DQ15
W14
SDR_DQ14
D
R
_
D
Q
1
3
A
V14
M3
SDR_DQ13
ARM_A22
ARM_A21
P13
L7
SDR_DQ12
ARM_A21
ARM_A20
R13
M5
SDR_DQ11
ARM_A20
ARM_A19
W15
N1
SDR_DQ10
ARM_A19
ARM_A18
U14
N2
SDR_DQ9
ARM_A18
ARM_A17
V15
M6
ARM_A17
SDR_DQ8
ARM_A16
U15
N3
SDR_DQ7
ARM_A16
ARM_A15
W16
P1
SDR_DQ6
ARM_A15
ARM_A14
V16
M7
SDR_DQ5
ARM_A14
ARM_A13
U16
P2
SDR_DQ4
ARM_A13
ARM_A12
W17
N5
SDR_DQ3
ARM_A12
ARM_A11
V17
P3
SDR_DQ2
ARM_A11
ARM_A10
W18
R1
ARM_A10
SDR_DQ1
(LSB)
ARM_A9
U17
R2
SDR_DQ0
ARM_A9
ARM_A8
P5
ARM_A8
ARM_A7
R3
ARM_A7
ARM_A6
V5
T2
SDR_A14
ARM_A6
SDRAM BANK0
ARM_A5
W5
U2
SDR_A13
ARM_A5
SDRAM BANK1
ARM_A4
T3
ARM_A4
ARM_A3
R6
U1
SDR_A12
ARM_A3
(MSB)
ARM_A2
U6
V2
SDR_A11
ARM_A2
ARM_A1
V6
V1
SDR_A10
ARM_A1
ARM_A0
W6
U3
SDR_A9
ARM_A0
R7
SDR_A8
U7
SDR_A7
V7
SDR_A6
W7
SDR_A5
P7
F3
SDR_A4
CFOE
R8
E2
SDR_A3
CFE0
U8
F5
SDR_A2
CFE1
V8
SDR_A1
(LSB)
P8
SDR_A0
G3
CF_WAIT
H3
CFRDY
F1
IOIS16
W9
G5
SDR_CLK
CFIORD
R9
F2
SDR_CS
CFIOWD
N9
SDR_RAS
W8
SDR_CAS
P9
N17
SDR_WE
MS/SD_DATA3
U9
M15
SDR_CKE
MS/SD_DATA2
N10
N18
SDR_DQM3
MS/SD_DATA1
N11
N19
SDR_DQM2
MS/SD_DATA0
U10
P19
MS/SD_CLK
SDR_DQM1
V10
M13
SDR_DQM0
MS_STATE/SD_CMD
EH_BMUX
J3
EM_BMUX
EM_WAIT
G6
EM_WAIT
EM_BEL
G2
EM_BEL
EM_BEH
G7
EM_BEH
G1
EM_CE0
H5
EM_CE1
E1
EM_WE
G8
EM_OE
D1
FLSH_CE
H1
BUSWIDTH
TMSDM320ZHK
ARM_D12
1
ARM_D11
2
ARM_D14
3
ARM_D15
4
5
ARM_D0
1
ARM_D[15:0]
ARM_D15
ARM_D3
2
ARM_D14
ARM_D1
3
ARM_D13
A
R
M
_
D
2
4
ARM_D12
5
ARM_D11
ARM_D10
ARM_D9
ARM_D8
ARM_D7
ARM_D6
ARM_D5
ARM_D4
ARM_D3
ARM_A18
1
ARM_D2
ARM_A19
2
ARM_D1
ARM_A22
3
ARM_D0
ARM_A21
4
5
ARM_A[22:0]
R
M
_
A
2
2
ARM_A10
1
ARM_A13
2
ARM_A15
3
ARM_A14
4
5
ARM_A0
1
ARM_A5
2
ARM_A3
3
ARM_A6
4
5
+3.3V
PR1
10K 5% 1005
CFWAIT
CFRDY
IOIS16
CFIORD
CFRDY
CFIOWR
IOIS16
CFIORD
CFIOWR
RNP11
R80
47K 5% 1005
EM_WE
1
EM_BEH
2
EM_BEL
3
4
CE0
5
EM_WE
EM_WE
EM_OE
EM_OE
47K 5% PULL-UP/DOWN REG 1608X5
FLSH_CE
BUSWIDTH
Tuesday, June 28, 2005
RNP5
+3.3V
10
ARM_D10
9
ARM_D8
8
ARM_D13
7
ARM_D9
6
47K 5% PULL-UP/DOWN REG 1608X5
RNP6
+3.3V
10
ARM_D7
9
ARM_D4
8
A
R
M
_
D
6
7
ARM_D5
6
47K 5% PULL-UP/DOWN REG 1608X5
RNP7
+3.3V
10
ARM_A16
9
ARM_A17
8
ARM_A20
7
6
47K 5% PULL-UP/DOWN REG 1608X5
RNP8
+3.3V
10
ARM_A9
9
ARM_A8
8
ARM_A11
7
ARM_A12
6
47K 5% PULL-UP/DOWN REG 1608X5
RNP9
+3.3V
10
ARM_A4
9
ARM_A7
8
ARM_A2
7
ARM_A1
6
47K 5% PULL-UP/DOWN REG 1608X5
+3.3V
RNP10
1
8
2
7
3
6
4
5
10K ARRAY 5% 1608X4
+3.3V
10
9
EM_WAIT
8
EM_OE
7
6
Werbung
Inhaltsverzeichnis
